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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 137kb
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  • Author :oup***
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Introduction - If you have any usage issues, please Google them yourself
A RS232 computer interface implementation with FPGA-based VHDL language communications designed a very simple procedure
Packet file list
(Preview for download)
uart01
......\automake.log
......\baud.vhd
......\pepExtractor.prj
......\reciever.vhd
......\results.txt
......\tb_uart.ant
......\tb_uart.fdo
......\tb_uart.jhd
......\tb_uart.tbw
......\tb_uart.udo
......\tb_uart.vhw
......\tb_uart.xwv_bak
......\tb_uart_bencher.prj
......\top.cmd_log
......\top.lso
......\top.ngc
......\top.ngr
......\top.prj
......\top.stx
......\top.syr
......\top_summary.html
......\transcript
......\transfer.vhd
......\uart.vhd
......\uart01.dhp
......\uart01.ise
......\uart01.ise_ISE_Backup
......\vsim.wlf
......\work
......\....\baud
......\....\....\behavioral.asm
......\....\....\behavioral.dat
......\....\....\_primary.dat
......\....\reciever
......\....\........\behavioral.asm
......\....\........\behavioral.dat
......\....\........\_primary.dat
......\....\tb_uart
......\....\.......\testbench_arch.asm
......\....\.......\testbench_arch.dat
......\....\.......\_primary.dat
......\....\top
......\....\...\behavioral.asm
......\....\...\behavioral.dat
......\....\...\_primary.dat
......\....\transfer
......\....\........\behavioral.asm
......\....\........\behavioral.dat
......\....\........\_primary.dat
......\....\_info
......\xst
......\...\dump.xst
......\...\........\top.prj
......\...\........\.......\ngx
......\...\........\.......\...\notopt
......\...\........\.......\...\opt
......\...\work
......\...\....\hdllib.ref
......\...\....\hdpdeps.ref
......\...\....\sub00
......\...\....\.....\vhpl00.vho
......\...\....\.....\vhpl01.vho
......\...\....\.....\vhpl02.vho
......\...\....\.....\vhpl03.vho
......\...\....\.....\vhpl04.vho
......\...\....\.....\vhpl05.vho
......\...\....\.....\vhpl06.vho
......\...\....\.....\vhpl07.vho
......\_xmsgs
......\__ISE_repository_uart01.ise_.lock
......\__projnav
......\.........\runXst_tcl.rsp
......\.........\sumrpt_tcl.rsp
......\.........\top.xst
......\.........\uart01.gfl
......\.........\uart01_flowplus.gfl
......\__projnav.log
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