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div(FLP)

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 18kb
  • Downloaded :0次
  • Author :T****
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Introduction - If you have any usage issues, please Google them yourself
Nios II processors are customized instruction under a 32-bit floating-point divider can be two format IEEE 754 value division
Packet file list
(Preview for download)
div(FLP)
........\conv.vhd
........\csa_1bit.vhd
........\csa_1weight_odd.vhd
........\csa_2weight.vhd
........\cube24.vhd
........\fa_1bit.vhd
........\fpdivider24.vhd
........\fpdivider24_v1.vhd
........\fpdiv_32.vhd
........\index.vhd
........\msub24_1bx_shell.vhd
........\mult_ax.vhd
........\mult_final28.vhd
........\mult_sub24_1bx.vhd
........\rca_20bit.vhd
........\square24.vhd
........\sum28.vhd
........\sum28_shell.vhd
........\table.vhd
........\table_shell.vhd
........\transcript
........\truncate.vhd
........\vish_stacktrace.vstf
........\words.vhd
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