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perfect_machine_yeat

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 46kb
  • Downloaded :0次
  • Author :four*****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
阿斯顿发时发生大幅 发撒旦发生大法沙发沙发沙发大事发生的发生的发生的方式大法大法师父啊
Packet file list
(Preview for download)
同步4×4加法器
..............\counter_16b.v
..............\counter_16b.v.bak
..............\counter_4b.v
..............\counter_4b.v.bak
..............\tcounter_16b.v
..............\tcounter_16b.v.bak
同步4位加法器
.............\counter_4b.v
.............\tcounter_4b.v
四位寄存器以及测试
..................\hardreg.txt
..................\thardreg.txt
期末作业
........\tuart_rec.v
........\tuart_rec.v.bak
........\uart_rec.v
........\uart_rec.v.bak
........\Verilog 期末大作业.doc
........\复件 tuart_rec.txt
........\复件 uart_rec.txt
状态机
......\fsm.txt
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