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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 133kb
  • Downloaded :0次
  • Author :张****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
The document is a VHDL implementation of the digital clock into the procedure, please advise!
Packet file list
(Preview for download)
szz
...\db
...\..\prev_cmp_szsz.asm.qmsg
...\..\prev_cmp_szsz.fit.qmsg
...\..\prev_cmp_szsz.map.qmsg
...\..\prev_cmp_szsz.qmsg
...\..\prev_cmp_szsz.tan.qmsg
...\..\szsz.asm.qmsg
...\..\szsz.cbx.xml
...\..\szsz.cmp.cdb
...\..\szsz.cmp.hdb
...\..\szsz.cmp.logdb
...\..\szsz.cmp.rdb
...\..\szsz.cmp.tdb
...\..\szsz.cmp0.ddb
...\..\szsz.db_info
...\..\szsz.eco.cdb
...\..\szsz.fit.qmsg
...\..\szsz.hier_info
...\..\szsz.hif
...\..\szsz.map.cdb
...\..\szsz.map.hdb
...\..\szsz.map.logdb
...\..\szsz.map.qmsg
...\..\szsz.pre_map.cdb
...\..\szsz.pre_map.hdb
...\..\szsz.rtlv.hdb
...\..\szsz.rtlv_sg.cdb
...\..\szsz.rtlv_sg_swap.cdb
...\..\szsz.sgdiff.cdb
...\..\szsz.sgdiff.hdb
...\..\szsz.sld_design_entry.sci
...\..\szsz.sld_design_entry_dsc.sci
...\..\szsz.syn_hier_info
...\..\szsz.tan.qmsg
...\..\szsz.tis_db_list.ddb
...\..\szsz.tmw_info
...\hour.bsf
...\hour.vhd
...\minute.bsf
...\minute.vhd
...\second.bsf
...\second.vhd
...\szsz.asm.rpt
...\szsz.done
...\szsz.fit.rpt
...\szsz.fit.summary
...\szsz.flow.rpt
...\szsz.map.rpt
...\szsz.map.summary
...\szsz.pin
...\szsz.pof
...\szsz.qpf
...\szsz.qsf
...\szsz.qws
...\szsz.sof
...\szsz.tan.rpt
...\szsz.tan.summary
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