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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 200kb
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  • Author :jiang******
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Introduction - If you have any usage issues, please Google them yourself
Simple i/O interface of the VHDL design, including engineering, source code, simulation waveforms, for the POC-based interface
Packet file list
(Preview for download)
pocp
....\db
....\..\pocp.asm.qmsg
....\..\pocp.asm_labs.ddb
....\..\pocp.cbx.xml
....\..\pocp.cmp.cdb
....\..\pocp.cmp.hdb
....\..\pocp.cmp.qrpt
....\..\pocp.cmp.rdb
....\..\pocp.cmp.tdb
....\..\pocp.cmp0.ddb
....\..\pocp.dbp
....\..\pocp.db_info
....\..\pocp.eco.cdb
....\..\pocp.eds_overflow
....\..\pocp.fit.qmsg
....\..\pocp.fnsim.cdb
....\..\pocp.fnsim.hdb
....\..\pocp.fnsim.qmsg
....\..\pocp.hier_info
....\..\pocp.hif
....\..\pocp.map.cdb
....\..\pocp.map.hdb
....\..\pocp.map.qmsg
....\..\pocp.pre_map.cdb
....\..\pocp.pre_map.hdb
....\..\pocp.psp
....\..\pocp.rtlv.hdb
....\..\pocp.rtlv_sg.cdb
....\..\pocp.rtlv_sg_swap.cdb
....\..\pocp.sgdiff.cdb
....\..\pocp.sgdiff.hdb
....\..\pocp.signalprobe.cdb
....\..\pocp.sim.hdb
....\..\pocp.sim.qmsg
....\..\pocp.sim.qrpt
....\..\pocp.sim.rdb
....\..\pocp.sim.vwf
....\..\pocp.sld_design_entry.sci
....\..\pocp.sld_design_entry_dsc.sci
....\..\pocp.syn_hier_info
....\..\pocp.tan.qmsg
....\POC.bsf
....\POC.vhd
....\pocp.asm.rpt
....\pocp.bdf
....\pocp.done
....\pocp.fit.eqn
....\pocp.fit.rpt
....\pocp.fit.summary
....\pocp.flow.rpt
....\pocp.map.eqn
....\pocp.map.rpt
....\pocp.map.summary
....\pocp.pin
....\pocp.pof
....\pocp.qpf
....\pocp.qsf
....\pocp.qws
....\pocp.sim.rpt
....\pocp.tan.rpt
....\pocp.tan.summary
....\pocp.vwf
....\printer.bdf
....\printer.bsf
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