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200441123245276683

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 325kb
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  • Author :shuang******
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Introduction - If you have any usage issues, please Google them yourself
VHDL
Packet file list
(Preview for download)
200441123245276683
..................\200441123245276683
..................\..................\100vhdl例子
..................\..................\...........\10_function
..................\..................\...........\...........\10_bit_to_int.vhd
..................\..................\...........\...........\README.TXT
..................\..................\...........\11_wiredor
..................\..................\...........\..........\11_wiredor.vhd
..................\..................\...........\..........\README.TXT
..................\..................\...........\12_convert
..................\..................\...........\..........\12_convert.vhd
..................\..................\...........\..........\README.TXT
..................\..................\...........\13_SHL
..................\..................\...........\......\13_SHL.VHD
..................\..................\...........\......\README.TXT
..................\..................\...........\14_MVL7_functions
..................\..................\...........\.................\14_MVL7_functions.vhd
..................\..................\...........\.................\README.TXT
..................\..................\...........\15_MUX41
..................\..................\...........\........\15_MUX41.VHD
..................\..................\...........\........\15_MVL7_functions.vhd
..................\..................\...........\........\15_MVL7_syn_types.vhd
..................\..................\...........\........\15_test_vectors_mux41.vhd
..................\..................\...........\........\15_TYPES.VHD
..................\..................\...........\........\README.TXT
..................\..................\...........\16_MUX
..................\..................\...........\......\16_multiple_mux.vhd
..................\..................\...........\......\16_MVL7_functions.vhd
..................\..................\...........\......\16_test_vectors.vhd
..................\..................\...........\......\16_TYPES.VHD
..................\..................\...........\......\README.TXT
..................\..................\...........\......\TYPES.VHD
..................\..................\...........\17_parity
..................\..................\...........\.........\17_parity.vhd
..................\..................\...........\.........\17_test_bench.vhd
..................\..................\...........\.........\README.TXT
..................\..................\...........\18_LIB
..................\..................\...........\......\18_tech_lib.vhd
..................\..................\...........\......\18_test_lib.vhd
..................\..................\...........\......\README.TXT
..................\..................\...........\19_test_194
..................\..................\...........\...........\19_test_194.vhd
..................\..................\...........\1_ADDER
..................\..................\...........\.......\1_ADDER
..................\..................\...........\.......\.......\1_ADDER.exp
..................\..................\...........\.......\.......\files
..................\..................\...........\.......\.......\.....\L1.rpt
..................\..................\...........\.......\.......\.....\L2.rpt
..................\..................\...........\.......\.......\.....\L3.rpt
..................\..................\...........\.......\.......\workdirs
..................\..................\...........\.......\.......\........\aa
..................\..................\...........\.......\.......\........\..\ADDER.sim
..................\..................\...........\.......\.......\........\..\ADDER.syn
..................\..................\...........\.......\.......\........\..\Anal.info
..................\..................\...........\.......\.......\........\..\Anal.out
..................\..................\...........\.......\.......\........\WORK
..................\..................\...........\.......\.......\........\....\Anal.info
..................\.............
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