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qiangdaqi

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 1.05mb
  • Downloaded :1次
  • Author :叶**
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Introduction - If you have any usage issues, please Google them yourself
Answer using Verilog prepared, and when the host announced the " start game" , the system initialization, players enter the " Answer status." When a player first of all, press the Answer the switch, the corresponding indicator light, when the Answer Explorer no longer accept other input signals. Circuit with a total of sub-control (separately with four players four points- hexadecimal number), by the host control " points." " Add points" add hours after beginning the next round of Answer. Circuit can also be equipped with time control to answer questions.
Packet file list
(Preview for download)
qiangdaqi
.........\.lso
.........\adder.v
.........\ban.v
.........\control.ngc
.........\control.ngr
.........\control.prj
.........\control.stx
.........\control.v
.........\control.xst
.........\control_stx.prj
.........\control_vhdl.prj
.........\counter.prj
.........\counter.stx
.........\counter.v
.........\counter.xst
.........\counter_vhdl.prj
.........\dchu.prj
.........\dchu.stx
.........\dchu.v
.........\dchu.xst
.........\dchu_vhdl.prj
.........\display.prj
.........\display.stx
.........\display.v
.........\display.xst
.........\display_vhdl.prj
.........\fen.prj
.........\fen.stx
.........\fen.v
.........\fen.xst
.........\fen_vhdl.prj
.........\full.v
.........\isim
.........\....\temp
.........\....\....\hdllib.ref
.........\....\....\hdpdeps.ref
.........\....\....\vlg10
.........\....\....\.....\counter.bin
.........\....\....\vlg1E
.........\....\....\.....\display.bin
.........\....\....\vlg2D
.........\....\....\.....\glbl.bin
.........\....\....\vlg57
.........\....\....\.....\qiangdaqi.bin
.........\....\....\vlg61
.........\....\....\.....\control.bin
.........\....\work
.........\....\....\control
.........\....\....\.......\control.h
.........\....\....\.......\mingw
.........\....\....\.......\.....\control.obj
.........\....\....\counter
.........\....\....\.......\counter.h
.........\....\....\.......\mingw
.........\....\....\.......\.....\counter.obj
.........\....\....\display
.........\....\....\.......\display.h
.........\....\....\.......\mingw
.........\....\....\.......\.....\display.obj
.........\....\....\glbl
.........\....\....\....\glbl.h
.........\....\....\....\mingw
.........\....\....\....\.....\glbl.obj
.........\....\....\hdllib.ref
.........\....\....\hdpdeps.ref
.........\....\....\q
.........\....\....\.\mingw
.........\....\....\.\.....\q.obj
.........\....\....\.\q.h
.........\....\....\.\xsimq.cpp
.........\....\....\qiangdaqi
.........\....\....\.........\mingw
.........\....\....\.........\.....\qiangdaqi.obj
.........\....\....\.........\qiangdaqi.h
.........\....\....\vlg10
.........\....\....\.....\counter.bin
.........\....\....\vlg1E
.........\....\....\.....\display.bin
.........\....\....\vlg2D
.........\....\....\.....\glbl.bin
.........\....\....\vlg57
.........\....\....\.....\qiangdaqi.bin
.........\....\....\vlg61
.........\....\....\.....\control.bin
.........\....\....\vlg71
.........\....\....\.....\q.bin
.........\isim.cmd
.........\isim.hdlsourcefiles
.........\isim.log
.........\isim.tmp_save
.........\.............\_1
.........\isimwavedata.xwv
.........\prjname.lso
.........\q.ant
.........\q.jhd
.........\q.tbw
.........\q.tfw
.........\q.xwv
.........\q.xwv_bak
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