Implement a 10-second countdown timer and require 8*8 to display timing results. On the QuartusII platform, the design procedure and simulation title are required, and the experimental results are downloaded to the experimental board. In the design process and simulation on the subject request and download to the board to verify the experimental results.

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...\db
...\..\cmp_state.ini
...\..\db
...\..\..\dianzhen.asm.qmsg
...\..\..\dianzhen.cmp.cdb
...\..\..\dianzhen.cmp.ddb
...\..\..\dianzhen.cmp.hdb
...\..\..\dianzhen.cmp.rdb
...\..\..\dianzhen.cmp.tdb
...\..\..\dianzhen.dat_manager.dat
...\..\..\dianzhen.db_info
...\..\..\dianzhen.fit.qmsg
...\..\..\dianzhen.hier_info
...\..\..\dianzhen.hif
...\..\..\dianzhen.icc
...\..\..\dianzhen.map.cdb
...\..\..\dianzhen.map.hdb
...\..\..\dianzhen.map.qmsg
...\..\..\dianzhen.pre_map.hdb
...\..\..\dianzhen.project.hdb
...\..\..\dianzhen.rtlv.hdb
...\..\..\dianzhen.rtlv_sg.cdb
...\..\..\dianzhen.rtlv_sg_swap.cdb
...\..\..\dianzhen.sgdiff.cdb
...\..\..\dianzhen.sgdiff.hdb
...\..\..\dianzhen.signalprobe.cdb
...\..\..\dianzhen.sim.hdb
...\..\..\dianzhen.sim.qmsg
...\..\..\dianzhen.sim.rdb
...\..\..\dianzhen.sim.vwf
...\..\..\dianzhen.sld_design_entry.sci
...\..\..\dianzhen.sld_design_entry_dsc.sci
...\..\..\dianzhen.syn_hier_info
...\..\..\dianzhen.tan.qmsg
...\..\..\dianzhen_cmp.qrpt
...\..\..\dianzhen_sim.qrpt
...\..\dianzhen.asm.rpt
...\..\dianzhen.done
...\..\dianzhen.fit.eqn
...\..\dianzhen.fit.rpt
...\..\dianzhen.fit.summary
...\..\dianzhen.flow.rpt
...\..\dianzhen.map.eqn
...\..\dianzhen.map.rpt
...\..\dianzhen.map.summary
...\..\dianzhen.pin
...\..\dianzhen.qpf
...\..\dianzhen.qsf
...\..\dianzhen.qws
...\..\dianzhen.sim.rpt
...\..\dianzhen.tan.rpt
...\..\dianzhen.tan.summary
...\..\dianzhen.vhd
...\..\dianzhen.vwf
...\..\sim.cfg
数电实验报告.doc

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