Using Block RAM for High-Performance Read.Write Cams

Verilog
.......\cam_generic_8s.v
.......\cam_ramb4.v
.......\CAM_Top.ucf
.......\cam_top.v
.......\Decode_1.v
.......\Decode_2.v
.......\Decode_3.v
.......\Decode_4.v
.......\encode_1_msb.v
.......\encode_2_msb.v
.......\encode_3_msb.v
.......\encode_4_lsb.v
.......\encode_4_msb.v
.......\init_8_ram16x1s.v
.......\init_ramb4_s1_s16.v
.......\parameters.v
.......\readme.txt
.......\tb_cam_ramb4.v
Vhdl
....\CAM_generic_8s.vhd
....\CAM_RAMB4.vhd
....\CAM_Top.ucf
....\CAM_top.vhd
....\Decode_1.vhd
....\Decode_2.vhd
....\Decode_3.vhd
....\Decode_4.vhd
....\Encode_1_MSB.vhd
....\Encode_2_MSB.vhd
....\Encode_3_MSB.vhd
....\Encode_4_LSB.vhd
....\Encode_4_MSB.vhd
....\Init_8_RAM16x1s.vhd
....\Init_RAMB4_S1_S16.vhd
....\readme.txt
....\TB_CAM_RAMB4.vhd

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