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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 230kb
  • Downloaded :0次
  • Author :r*****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
8 Channel Digital Volt Meter
Packet file list
(Preview for download)
8chDVM.prc
readme.txt
Source
......\PocketC
......\.......\8chDVM.c

......\.......\Xilinx.bmp
......\VHDL
......\....\automake.log
......\....\last_used.ucf
......\....\multi_dvm.jhd
......\....\multi_dvm.vhd
......\....\multi_dvm_tb.jhd
......\....\multi_dvm_tb.vhd
......\....\shift16.jhd
......\....\shift16.vhd
......\....\shift8.jhd
......\....\shift8.vhd
......\....\top_level.ann
......\....\top_level.baf
......\....\top_level.blx
......\....\top_level.cxt
......\....\top_level.jhd
......\....\top_level.log
......\....\top_level.mfd
......\....\top_level.paf
......\....\top_level.ph0
......\....\top_level.ph1
......\....\top_level.ph2
......\....\top_level.prt
......\....\top_level.ucf
......\....\top_level.vhd
......\....\top_level_tb.jhd
......\....\top_level_tb.udo
......\....\top_level_tb.vhd
......\....\top_level_timesim.sdf
......\....\top_level_timesim.vhd
......\....\upcnt5.jhd
......\....\upcnt5.vhd
......\....\vhdl.jid
......\....\vhdl.npl
......\....\__filesAllClean.fac
......\....\__projnav.log
top_level.jed
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