LVDS transmission between the FPGA using serdes interface, transfer rate up to 400m

LVDS_Serdes_list_FPGA1
......................\bit_align_machine.bgn
......................\BIT_ALIGN_MACHINE.bld
......................\bit_align_machine.drc
......................\BIT_ALIGN_MACHINE.ncd
......................\BIT_ALIGN_MACHINE.ngd
......................\BIT_ALIGN_MACHINE.pad
......................\BIT_ALIGN_MACHINE.par
......................\BIT_ALIGN_MACHINE.pcf
......................\BIT_ALIGN_MACHINE.ptwx
......................\BIT_ALIGN_MACHINE.twr
......................\BIT_ALIGN_MACHINE.twx
......................\BIT_ALIGN_MACHINE.unroutes
......................\BIT_ALIGN_MACHINE.ut
......................\BIT_ALIGN_MACHINE.v
......................\BIT_ALIGN_MACHINE.vhd
......................\BIT_ALIGN_MACHINE.vhd.bak
......................\BIT_ALIGN_MACHINE.xpi
......................\BIT_ALIGN_MACHINE_guide.ncd
......................\BIT_ALIGN_MACHINE_map.map
......................\BIT_ALIGN_MACHINE_map.mrp
......................\BIT_ALIGN_MACHINE_map.ncd
......................\BIT_ALIGN_MACHINE_map.ngm
......................\BIT_ALIGN_MACHINE_map.xrpt
......................\BIT_ALIGN_MACHINE_ngdbuild.xrpt
......................\BIT_ALIGN_MACHINE_pad.csv
......................\BIT_ALIGN_MACHINE_pad.txt
......................\BIT_ALIGN_MACHINE_par.xrpt
......................\BIT_ALIGN_MACHINE_prev_built.ngd
......................\BIT_ALIGN_MACHINE_summary.html
......................\BIT_ALIGN_MACHINE_summary.xml
......................\BIT_ALIGN_MACHINE_usage.xml
......................\BIT_ALIGN_MACHINE_xst.xrpt
......................\bypass_bram.v
......................\count_to_128.vhd
......................\count_to_16x.vhd
......................\COUNT_TO_64.vhd
......................\CS.cdc
......................\DDR_6TO1_16CHAN_RT_RX.bld
......................\DDR_6TO1_16CHAN_RT_RX.ncd
......................\DDR_6TO1_16CHAN_RT_RX.ngc
......................\DDR_6TO1_16CHAN_RT_RX.ngd
......................\DDR_6TO1_16CHAN_RT_RX.ngr
......................\DDR_6TO1_16CHAN_RT_RX.pad
......................\DDR_6TO1_16CHAN_RT_RX.par
......................\DDR_6TO1_16CHAN_RT_RX.pcf
......................\DDR_6TO1_16CHAN_RT_RX.ptwx
......................\DDR_6TO1_16CHAN_RT_RX.twr
......................\DDR_6TO1_16CHAN_RT_RX.twx
......................\DDR_6TO1_16CHAN_RT_RX.udo
......................\DDR_6TO1_16CHAN_RT_RX.unroutes
......................\DDR_6TO1_16CHAN_RT_RX.v3
......................\DDR_6TO1_16CHAN_RT_RX.vhd
......................\DDR_6TO1_16CHAN_RT_RX.vhd.bak
......................\DDR_6TO1_16CHAN_RT_RX.xpi
......................\DDR_6TO1_16CHAN_RT_RX2.vhd
......................\DDR_6TO1_16CHAN_RT_RX_fpga_editor.out
......................\DDR_6TO1_16CHAN_RT_RX_guide.ncd
......................\DDR_6TO1_16CHAN_RT_RX_map.map
......................\DDR_6TO1_16CHAN_RT_RX_map.mrp
......................\DDR_6TO1_16CHAN_RT_RX_map.ncd
......................\DDR_6TO1_16CHAN_RT_RX_map.ngm
......................\DDR_6TO1_16CHAN_RT_RX_map.xrpt
......................\DDR_6TO1_16CHAN_RT_RX_ngdbuild.xrpt
......................\DDR_6TO1_16CHAN_RT_RX_pad.csv
......................\DDR_6TO1_16CHAN_RT_RX_pad.txt
......................\DDR_6TO1_16CHAN_RT_RX_par.xrpt
......................\DDR_6TO1_16CHAN_RT_RX_prev_built.ngd
......................\DDR_6TO1_16CHAN_RT_RX_summary.html
......................\DDR_6TO1_16CHAN_RT_RX_summary.xml
......................\DDR_6TO1_16CHAN_RT_RX_usage.xml
......................\DDR_6TO1_16CHAN_RT_RX_wave.fdo
......................\DDR_6TO1_16CHAN_RT_RX_xst.xrpt
......................\DDR_6TO1_16CHAN_RT_TX.bld
......................\DDR_6TO1_16CHAN_RT_TX.ncd
......................\DDR_6TO1_16CHAN_RT_TX.ngc
......................\DDR_6TO1_16CHAN_RT_TX.ngd
......................\DDR_6TO1_16CHAN_RT_TX.ngr
......................\DDR_6TO1_16CHAN_RT_TX.pad
......................\DDR_6TO1_16CHAN_RT_TX.par
......................\DDR_6TO1_16CHAN_RT_TX.pcf
......................\DDR_6TO1_16CHAN_RT_TX.ptwx
......................\DDR_6TO1_16CHAN_RT_TX.twr
......................\DDR_6T

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