Introduction - If you have any usage issues, please Google them yourself
This guide is intended for the engineer who is familiar with the principles of
hardware design, but has little experience in designing with a language-based
synthesis system. It describes the general concepts of synthesis, the general
organization and usage of VHDL, and provides specific information on how the
Metamor tool is used in this environment. It does not attempt to present the VHDL
language in depth, but does provide an example-based summary of VHDL syntax
that serves as a helpful reference for any user.