Introduction - If you have any usage issues, please Google them yourself
FPGA/CPLD applications, UART communications VHDL source.
Packet : 7941953altera_uart_vhdl.zip filelist
address_decode_rtl.vhd
clock_divider.v
control_operation_fsm.vhd
cpu_interface_rtl.vhd
serial_interface_rtl.vhd
status_registers_rtl.vhd
tester.v
uart_tb.v
uart_top_rtl.vhd
xmit_rcv_control_fsm.vhd