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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 10.34mb
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  • Author :袁****
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Introduction - If you have any usage issues, please Google them yourself
With four decimal counter input clock signal to the user to count, count one second interval. 1 seconds after the full count of values (that is, the frequency value) stored in the register to display 4, and Counter-ching 0, the time of the next count. Frequency of three modules: testctl for the control module, the alignment of 1Hz generated by rst_cnt, load, cnt_en signal cnt10 with clearance for the count 0 and the decimal counter permit reg4b register for the four.
Packet file list
(Preview for download)
lianxi5
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