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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 285kb
  • Downloaded :0次
  • Author :小***
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Butterfly song
Packet file list
(Preview for download)
gequ
....\Block1.bdf
....\clockdiv4.bsf
....\clockdiv4.vhd
....\db
....\..\gequ.asm.qmsg
....\..\gequ.asm_labs.ddb
....\..\gequ.cbx.xml
....\..\gequ.cmp.cdb
....\..\gequ.cmp.hdb
....\..\gequ.cmp.logdb
....\..\gequ.cmp.rdb
....\..\gequ.cmp.tdb
....\..\gequ.cmp0.ddb
....\..\gequ.dbp
....\..\gequ.db_info
....\..\gequ.eco.cdb
....\..\gequ.fit.qmsg
....\..\gequ.hier_info
....\..\gequ.hif
....\..\gequ.map.cdb
....\..\gequ.map.hdb
....\..\gequ.map.logdb
....\..\gequ.map.qmsg
....\..\gequ.pre_map.cdb
....\..\gequ.pre_map.hdb
....\..\gequ.psp
....\..\gequ.pss
....\..\gequ.rtlv.hdb
....\..\gequ.rtlv_sg.cdb
....\..\gequ.rtlv_sg_swap.cdb
....\..\gequ.sgdiff.cdb
....\..\gequ.sgdiff.hdb
....\..\gequ.signalprobe.cdb
....\..\gequ.sld_design_entry.sci
....\..\gequ.sld_design_entry_dsc.sci
....\..\gequ.syn_hier_info
....\..\gequ.tan.qmsg
....\..\gequ.tis_db_list.ddb
....\..\prev_cmp_gequ.asm.qmsg
....\..\prev_cmp_gequ.fit.qmsg
....\..\prev_cmp_gequ.map.qmsg
....\..\prev_cmp_gequ.qmsg
....\..\prev_cmp_gequ.tan.qmsg
....\gequ.asm.rpt
....\gequ.bsf
....\gequ.cdf
....\gequ.done
....\gequ.dpf
....\gequ.fit.rpt
....\gequ.fit.smsg
....\gequ.fit.summary
....\gequ.flow.rpt
....\gequ.map.rpt
....\gequ.map.summary
....\gequ.pin
....\gequ.pof
....\gequ.qpf
....\gequ.qsf
....\gequ.qws
....\gequ.tan.rpt
....\gequ.tan.summary
....\gequ.vhd
....\gequ.vhd.bak
....\spk.bsf
....\spk.vhd
....\spk.vhd.bak
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