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sdram_vhd

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 2.08mb
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Introduction - If you have any usage issues, please Google them yourself
FPGA Design of SDRAM controller, there is simulation code has been validated
Packet file list
(Preview for download)
sdram_vhd
.........\brst_cntr.vhd
.........\cslt_cntr.vhd
.........\functional_mti.do
.........\func_map_mti.do
.........\func_translate_mti.do
.........\f_sdrm_isim_par.exe
.........\f_sdrm_par.prj
.........\ihdlutil.vhd
.........\isim
.........\....\file graph
.........\....\simprim.auxlib
.........\....\..............\hdllib.ref
.........\....\..............\vcomponents
.........\....\..............\...........\mingw
.........\....\..............\...........\.....\vcomponents.obj
.........\....\..............\...........\vcomponents.h
.........\....\..............\vpackage
.........\....\..............\........\mingw
.........\....\..............\........\.....\vpackage.obj
.........\....\..............\........\vpackage.h
.........\....\..............\x_buf
.........\....\..............\.....\mingw
.........\....\..............\.....\.....\x_buf_v.obj
.........\....\..............\.....\x_buf_v.h
.........\....\..............\x_ckbuf
.........\....\..............\.......\mingw
.........\....\..............\.......\.....\x_ckbuf_v.obj
.........\....\..............\.......\x_ckbuf_v.h
.........\....\..............\x_dcm_adv
.........\....\..............\.........\mingw
.........\....\..............\.........\.....\x_dcm_adv_v.obj
.........\....\..............\.........\x_dcm_adv_v.h
.........\....\..............\x_dcm_adv_clock_divide_by_2
.........\....\..............\...........................\mingw
.........\....\..............\...........................\.....\x_dcm_adv_clock_divide_by_2_v.obj
.........\....\..............\...........................\x_dcm_adv_clock_divide_by_2_v.h
.........\....\..............\x_dcm_adv_clock_lost
.........\....\..............\....................\mingw
.........\....\..............\....................\.....\x_dcm_adv_clock_lost_v.obj
.........\....\..............\....................\x_dcm_adv_clock_lost_v.h
.........\....\..............\x_dcm_adv_maximum_period_check
.........\....\..............\..............................\mingw
.........\....\..............\..............................\.....\x_dcm_adv_maximum_period_check_v.obj
.........\....\..............\..............................\x_dcm_adv_maximum_period_check_v.h
.........\....\..............\x_ff
.........\....\..............\....\mingw
.........\....\..............\....\.....\x_ff_v.obj
.........\....\..............\....\x_ff_v.h
.........\....\..............\x_inv
.........\....\..............\.....\mingw
.........\....\..............\.....\.....\x_inv_v.obj
.........\....\..............\.....\x_inv_v.h
.........\....\..............\x_lut4
.........\....\..............\......\mingw
.........\....\..............\......\.....\x_lut4_v.obj
.........\....\..............\......\x_lut4_v.h
.........\....\..............\x_mux2
.........\....\..............\......\mingw
.........\....\..............\......\.....\x_mux2_v.obj
.........\....\..............\......\x_mux2_v.h
.........\....\..............\x_obuf
.........\....\..............\......\mingw
.........\....\..............\......\.....\x_obuf_v.obj
.........\....\..............\......\x_obuf_v.h
.........\....\..............\x_obuft
.........\....\..............\.......\mingw
.........\....\..............\.......\.....\x_obuft_v.obj
.........\....\..............\.......\x_obuft_v.h
.........\....\..............\x_one
.........\....\..............\.....\mingw
.........\....\..............\.....\.....\x_one_v.obj
.........\....\..............\.....\x_one_v.h
.........\....\..............\x_roc
.........\....\..............\.....\mingw
.........\....\..............\.....\.....\x_roc_v.obj
.........\....\..............\.....\x_roc_v.h
.........\....\..............\x_sff
.........\....\..............\.....\mingw
.........\....\..............\.....\.....\x_sff_v.obj
.........\....\..............\.....\x_sff_v.h
.........\....\..............\x_srlc16e
.........\....\..............\.........\mingw
.........\....\..............\.........\.....\x_srlc16e_v.obj
.........\....\..............\.........\x_srlc16e_v.h
.........\....\..............\x_toc
.........\....\.....
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