Series altera-based chip interface lvds source fpga design verilog

LVDS的应用的Verilog HDL例子程序(由Altera公司提供)
.................................................\sim
.................................................\...\comp_altera_lib.do
.................................................\...\comp_gate.do
.................................................\...\diff_io_top.vo
.................................................\...\diff_io_top_v.sdo
.................................................\...\gate_sim.do
.................................................\...\stratix
.................................................\...\.......\@p@r@i@m_@d@f@f@e
.................................................\...\.......\.................\verilog.asm
.................................................\...\.......\.................\_primary.dat
.................................................\...\.......\.................\_primary.vhd
.................................................\...\.......\and1
.................................................\...\.......\....\verilog.asm
.................................................\...\.......\....\_primary.dat
.................................................\...\.......\....\_primary.vhd
.................................................\...\.......\and16
.................................................\...\.......\.....\verilog.asm
.................................................\...\.......\.....\_primary.dat
.................................................\...\.......\.....\_primary.vhd
.................................................\...\.......\b17mux21
.................................................\...\.......\........\verilog.asm
.................................................\...\.......\........\_primary.dat
.................................................\...\.......\........\_primary.vhd
.................................................\...\.......\b5mux21
.................................................\...\.......\.......\verilog.asm
.................................................\...\.......\.......\_primary.dat
.................................................\...\.......\.......\_primary.vhd
.................................................\...\.......\bmux21
.................................................\...\.......\......\verilog.asm
.................................................\...\.......\......\_primary.dat
.................................................\...\.......\......\_primary.vhd
.................................................\...\.......\dffe
.................................................\...\.......\....\verilog.asm
.................................................\...\.......\....\_primary.dat
.................................................\...\.......\....\_primary.vhd
.................................................\...\.......\latch
.................................................\...\.......\.....\verilog.asm
.................................................\...\.......\.....\_primary.dat
.................................................\...\.......\.....\_primary.vhd
.................................................\...\.......\mux21
.................................................\...\.......\.....\verilog.asm
.................................................\...\.......\.....\_primary.dat
.................................................\...\.......\.....\_primary.vhd
.................................................\...\.......\m_cntr
.................................................\...\.......\......\verilog.asm
.................................................\...\.......\......\_primary.dat
.................................................\...\.......\......\_primary.vhd
.................................................\...\.......\nmux21
.................................................\...\.......\......\verilog.asm
.................................................\...\.......\......\_primary.dat
.................................................\...\.......\......\_primary.vhd
.................................................\...\.......\n_cntr
................................

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