The VHDLVERILOG language implementation of the CARDBUS IP source, has implemented the field application -CARDBUS IP CORE

verilog
.......\afifoflg.sch
.......\afifoflg.sym
.......\bus_chk.mem
.......\byte_enable_test.tf
.......\cardbus_5632.chp
.......\cardbus_5632.prj
.......\CARDBUS_5632.qcf
.......\CARDBUS_5632.qdf
.......\CARDBUS_5632.rpt
.......\CARDBUS_5632.sc
.......\cardbus_5632.sch
.......\CARDBUS_5632.scp
.......\CARDBUS_5632.sdf
.......\cardbus_5632.tf
.......\CARDBUS_5632.tre
.......\cardbus_5632.v
.......\CARDBUS_5632.vh
.......\CARDBUS_5632.vq
.......\cardbus_5632aldec.do
.......\cardbus_5632aldec_post.do
.......\cardbus_5632_modelsim.do
.......\cardbus_5632_modelsim_post.do
.......\cardbus_wrapper.sym
.......\cardbus_wrapper.tf
.......\cardbus_wrapper.v
.......\cardbus_wrapper_test.tf
.......\cfgtaddr_cardbus.sym
.......\cfgtaddr_cardbus.v
.......\cis_decode.sym
.......\CIS_decode.v
.......\cmd_monitor.tf
.......\ct_arbitration.tf
.......\ct_burst_latency_timeout.tf
.......\ct_burst_r_w.tf
.......\ct_burst_r_w_ws.tf
.......\ct_master.tf
.......\ct_parity_error.tf
.......\ct_single_r_w.tf
.......\ct_target.tf
.......\dcount16.v
.......\dcount8.v
.......\dffpa.sch
.......\dffpa.sym
.......\dmacntrl.sym
.......\dmacntrl.v
.......\dmaregrd.sym
.......\dmaregrd.v
.......\dma_test.tf
.......\ecomp5.sch
.......\ecomp5.sym
.......\f32a32_25um.sch
.......\f32a32_25um.sym
.......\f64x4.sym
.......\f64x4.v
.......\fifocont.sym
.......\fifocont.v
.......\gcnte5_0.sym
.......\gcnte5_0.v
.......\gcnte5_2.sym
.......\gcnte5_2.v
.......\gcnte5_3.sym
.......\gcnte5_3.v
.......\initflgs.sym
.......\initflgs.v
.......\pci5632_280.v
.......\pci_arb.tf
.......\pci_cmd_test.tf
.......\pci_mast.tf
.......\pci_tar.tf
.......\r128a8.v
.......\r128x32_25um.sym
.......\r128x32_25um.tf
.......\r128x32_25um.v
.......\r64x32.sym
.......\r64x32.v
.......\r64x4.v
.......\ram128x18_25um.sch
.......\ram128x18_25um.sym
.......\ram128x18_25um.v
.......\rgec5_1r.sym
.......\rgec5_1r.v
.......\rgec5_2.sym
.......\rgec5_2.v
.......\ucnt6.v
.......\updcnt6.v
vhdl
....\afifoflg.sch
....\afifoflg.sym
....\bus_chk.mem
....\byte_enable_test.tb
....\cardbus_5632.chp
....\cardbus_5632.prj
....\cardbus_5632.qcf
....\CARDBUS_5632.qdf
....\cardbus_5632.rpt
....\CARDBUS_5632.sc
....\cardbus_5632.sch
....\cardbus_5632.scp
....\cardbus_5632.sdf

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