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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 187kb
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  • Author :杨****
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4 shows the number of dynamic digital tube digital clock and seconds bit. Tools: Quartus ii 6.0 Language: VHDL
Packet file list
(Preview for download)
myled4
......\db
......\..\add_sub_97h.tdf
......\..\add_sub_nlh.tdf
......\..\myled4.asm.qmsg
......\..\myled4.cbx.xml
......\..\myled4.cmp.rdb
......\..\myled4.dbp
......\..\myled4.db_info
......\..\myled4.eco.cdb
......\..\myled4.fit.qmsg
......\..\myled4.hier_info
......\..\myled4.hif
......\..\myled4.map.cdb
......\..\myled4.map.hdb
......\..\myled4.map.logdb
......\..\myled4.map.qmsg
......\..\myled4.pre_map.cdb
......\..\myled4.pre_map.hdb
......\..\myled4.psp
......\..\myled4.rtlv.hdb
......\..\myled4.rtlv_sg.cdb
......\..\myled4.rtlv_sg_swap.cdb
......\..\myled4.sgdiff.cdb
......\..\myled4.sgdiff.hdb
......\..\myled4.sld_design_entry.sci
......\..\myled4.sld_design_entry_dsc.sci
......\..\myled4.syn_hier_info
......\..\myled4.tan.qmsg
......\myled4.asm.rpt
......\myled4.done
......\myled4.fit.rpt
......\myled4.fit.summary
......\myled4.flow.rpt
......\myled4.map.rpt
......\myled4.map.summary
......\myled4.pin
......\myled4.pof
......\myled4.qpf
......\myled4.qsf
......\myled4.qws
......\myled4.sof
......\myled4.tan.rpt
......\myled4.tan.summary
......\myled4.vhd
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