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Segment1

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 396kb
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  • Author :lizhu*****
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Introduction - If you have any usage issues, please Google them yourself
Register ep2c5 achieve above experiment a verilog language, quartus 2 Simulation
Packet file list
(Preview for download)
Segment1
........\Segment1
........\........\db
........\........\..\prev_cmp_Segment1.asm.qmsg
........\........\..\prev_cmp_Segment1.fit.qmsg
........\........\..\prev_cmp_Segment1.map.qmsg
........\........\..\prev_cmp_Segment1.qmsg
........\........\..\prev_cmp_Segment1.tan.qmsg
........\........\..\Segment1.asm.qmsg
........\........\..\Segment1.asm_labs.ddb
........\........\..\Segment1.cbx.xml
........\........\..\Segment1.cmp.bpm
........\........\..\Segment1.cmp.cdb
........\........\..\Segment1.cmp.ecobp
........\........\..\Segment1.cmp.hdb
........\........\..\Segment1.cmp.logdb
........\........\..\Segment1.cmp.rdb
........\........\..\Segment1.cmp.tdb
........\........\..\Segment1.cmp0.ddb
........\........\..\Segment1.cmp2.ddb
........\........\..\Segment1.db_info
........\........\..\Segment1.eco.cdb
........\........\..\Segment1.fit.qmsg
........\........\..\Segment1.hier_info
........\........\..\Segment1.hif
........\........\..\Segment1.map.bpm
........\........\..\Segment1.map.cdb
........\........\..\Segment1.map.ecobp
........\........\..\Segment1.map.hdb
........\........\..\Segment1.map.logdb
........\........\..\Segment1.map.qmsg
........\........\..\Segment1.map_bb.cdb
........\........\..\Segment1.map_bb.hdb
........\........\..\Segment1.map_bb.hdbx
........\........\..\Segment1.map_bb.logdb
........\........\..\Segment1.pre_map.cdb
........\........\..\Segment1.pre_map.hdb
........\........\..\Segment1.psp
........\........\..\Segment1.root_partition.cmp.atm
........\........\..\Segment1.root_partition.cmp.dfp
........\........\..\Segment1.root_partition.cmp.hdbx
........\........\..\Segment1.root_partition.cmp.logdb
........\........\..\Segment1.root_partition.cmp.rcf
........\........\..\Segment1.root_partition.map.atm
........\........\..\Segment1.root_partition.map.hdbx
........\........\..\Segment1.root_partition.map.info
........\........\..\Segment1.rtlv.hdb
........\........\..\Segment1.rtlv_sg.cdb
........\........\..\Segment1.rtlv_sg_swap.cdb
........\........\..\Segment1.sgdiff.cdb
........\........\..\Segment1.sgdiff.hdb
........\........\..\Segment1.signalprobe.cdb
........\........\..\Segment1.sld_design_entry.sci
........\........\..\Segment1.sld_design_entry_dsc.sci
........\........\..\Segment1.syn_hier_info
........\........\..\Segment1.tan.qmsg
........\........\..\Segment1.tis_db_list.ddb
........\........\..\Segment1.tmw_info
........\........\Segment1.asm.rpt
........\........\Segment1.done
........\........\Segment1.fit.rpt
........\........\Segment1.fit.smsg
........\........\Segment1.fit.summary
........\........\Segment1.flow.rpt
........\........\Segment1.map.rpt
........\........\Segment1.map.summary
........\........\Segment1.pin
........\........\Segment1.pof
........\........\Segment1.qpf
........\........\Segment1.qsf
........\........\Segment1.qws
........\........\Segment1.sof
........\........\Segment1.tan.rpt
........\........\Segment1.tan.summary
........\........\Segment1.v
........\........\Segment1.v.bak
........\........\Segment1_assignment_defaults.qdf
........\静态数码管显示.pdf
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