its a Fifo BASED design i also Interface DAC2904

FIFO_V2
.......\core
.......\....\ChipScope
.......\....\.........\icon.arg
.......\....\.........\icon.edn
.......\....\.........\icon.ncf
.......\....\.........\icon_xst_example.v
.......\....\.........\icon_xst_verilog_example.arg
.......\....\.........\ila.arg
.......\....\.........\ila.cdc
.......\....\.........\ila.edn
.......\....\.........\ila.ncf
.......\....\.........\ila_xst_example.v
.......\....\.........\ila_xst_verilog_example.arg
.......\....\FIFO
.......\....\....\coregen
.......\....\....\.......\coregen.cgp
.......\....\....\.......\FIFO_1Kx16.asy
.......\....\....\.......\FIFO_1Kx16.ngc
.......\....\....\.......\FIFO_1Kx16.sym
.......\....\....\.......\FIFO_1Kx16.v
.......\....\....\.......\FIFO_1Kx16.veo
.......\....\....\.......\FIFO_1Kx16.xco
.......\....\....\.......\FIFO_1Kx16_fifo_generator_v3_2_xst_1_vhdl.prj
.......\....\....\.......\FIFO_1Kx16_flist.txt
.......\....\....\.......\FIFO_1Kx16_readme.txt
.......\....\....\.......\FIFO_1Kx16_xmdf.tcl
.......\....\....\.......\fifo_generator_release_notes.txt
.......\....\....\.......\fifo_generator_ug175.pdf
.......\....\....\.......\tmp
.......\....\....\.......\...\_cg
.......\rtl
.......\...\clk_div.v
.......\...\clk_div.v.bak
.......\...\dac.v
.......\...\dac2904.v
.......\...\data_generator.v
.......\...\SDR.ucf
.......\...\SDR.ucf.bak
.......\...\timescale.v
.......\...\top.v
.......\...\top.v.bak
.......\sim
.......\...\fifo.cr.mti
.......\...\fifo.mpf
.......\...\FIFO_1Kx16.v
.......\...\FIFO_GENERATOR_V3_2.v
.......\...\SDR_TB.v
.......\...\tf_wave.v
.......\...\tf_wave.v.bak
.......\...\top_tb.v
.......\...\vsim.wlf
.......\...\work
.......\...\....\@f@i@f@o_1@kx16
.......\...\....\...............\verilog.asm
.......\...\....\...............\_primary.dat
.......\...\....\...............\_primary.vhd
.......\...\....\@f@i@f@o_@g@e@n@e@r@a@t@o@r_@v3_2
.......\...\....\.................................\verilog.asm
.......\...\....\.................................\_primary.dat
.......\...\....\.................................\_primary.vhd
.......\...\....\fifo_generator_v3_2_bhv_ver_as
.......\...\....\..............................\verilog.asm
.......\...\....\..............................\_primary.dat
.......\...\....\..............................\_primary.vhd
.......\...\....\fifo_generator_v3_2_bhv_ver_preload0
.......\...\....\....................................\verilog.asm
.......\...\....\....................................\_primary.dat
.......\...\....\....................................\_primary.vhd
.......\...\....\fifo_generator_v3_2_bhv_ver_ss
.......\...\....\..............................\verilog.asm
.......\...\....\..............................\_primary.dat
.......\...\....\..............................\_primary.vhd
.......\...\....\tf_wave_v
.......\...\....\.........\verilog.asm
.......\...\....\.........\_primary.dat
.......\...\....\.........\_primary.vhd
.......\...\....\_info
.......\syn
.......\...\.lso
.......\...\ChipScope.cpj
.......\...\clk_div.v
.......\...\dac.v
.......\...\dac2904.v
.......\...\data_generator.v
.......\...\FIFO_1Kx16.asy
.......\...\FIFO_1Kx16.ngc
.......\...\FIFO_1Kx16.ngc.bak
.......\...\FIFO_1Kx16.sym
.......\...\FIFO_1Kx16.v
.......\...\FIFO_1Kx16.veo
.......\...\FIFO_1Kx16.xco
.......\...\icon.arg
.......\...\icon.edn
.......\...\icon.ncf
.......\...\icon.ngo
.......\...\icon_xst_verilog_example.arg
.......\...\ila.arg
.......\...\ila.cdc
.......\...\ila.edn

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