VHDL language used to achieve a display hours, minutes and seconds of the clock: when can be manually corrected and points 12 hours, optional 24-hour time system, 12-hour on the afternoon of instructions from time to time when the time to the scheduled time (This time can be manually set), the speaker sent alarm signals, alarm time was 10 seconds, the alarm can be terminated prematurely.

myclock
.......\clk_and_modify.vhd
.......\cmp_state.ini
.......\db
.......\..\add_sub_5ph.tdf
.......\..\add_sub_rnh.tdf
.......\..\myclock.asm.qmsg
.......\..\myclock.cmp.cdb
.......\..\myclock.cmp.ddb
.......\..\myclock.cmp.hdb
.......\..\myclock.cmp.rdb
.......\..\myclock.cmp.tdb
.......\..\myclock.db_info
.......\..\myclock.fit.qmsg
.......\..\myclock.hier_info
.......\..\myclock.hif
.......\..\myclock.map.cdb
.......\..\myclock.map.hdb
.......\..\myclock.map.qmsg
.......\..\myclock.pre_map.hdb
.......\..\myclock.project.hdb
.......\..\myclock.rtlv.hdb
.......\..\myclock.rtlv_sg.cdb
.......\..\myclock.rtlv_sg_swap.cdb
.......\..\myclock.sgdiff.cdb
.......\..\myclock.sgdiff.hdb
.......\..\myclock.sim.hdb
.......\..\myclock.sim.qmsg
.......\..\myclock.sim.rdb
.......\..\myclock.sim.vwf
.......\..\myclock.sld_design_entry.sci
.......\..\myclock.sld_design_entry_dsc.sci
.......\..\myclock.syn_hier_info
.......\..\myclock.tan.qmsg
.......\..\myclock_cmp.qrpt
.......\..\myclock_sim.qrpt
.......\display.vhd
.......\distribute_frq.vhd
.......\myclock.asm.rpt
.......\myclock.cdf
.......\myclock.done
.......\myclock.fit.eqn
.......\myclock.fit.rpt
.......\myclock.fit.summary
.......\myclock.flow.rpt
.......\myclock.map.eqn
.......\myclock.map.rpt
.......\myclock.map.summary
.......\myclock.pin
.......\myclock.pof
.......\myclock.qpf
.......\myclock.qsf
.......\myclock.qws
.......\myclock.sim.rpt
.......\myclock.sim.vwf
.......\myclock.tan.rpt
.......\myclock.tan.summary
.......\myclock.vhd
.......\myclock.vwf
.......\sim.cfg
.......\time_form.vhd

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