A good example for VHDL study

comparator
..........\cmp.asm.rpt
..........\cmp.done
..........\cmp.fit.eqn
..........\cmp.fit.rpt
..........\cmp.fit.summary
..........\cmp.flow.rpt
..........\cmp.map.eqn
..........\cmp.map.rpt
..........\cmp.map.summary
..........\cmp.pin
..........\cmp.pof
..........\cmp.qpf
..........\cmp.qsf
..........\cmp.qws
..........\cmp.tan.rpt
..........\cmp.tan.summary
..........\cmp.vhd
..........\cmp_state.ini
..........\db
..........\..\cmp.asm.qmsg
..........\..\cmp.cbx.xml
..........\..\cmp.cmp.cdb
..........\..\cmp.cmp.hdb
..........\..\cmp.cmp.rdb
..........\..\cmp.cmp.tdb
..........\..\cmp.cmp0.ddb
..........\..\cmp.db_info
..........\..\cmp.eco.cdb
..........\..\cmp.fit.qmsg
..........\..\cmp.hier_info
..........\..\cmp.hif
..........\..\cmp.map.cdb
..........\..\cmp.map.hdb
..........\..\cmp.map.qmsg
..........\..\cmp.pre_map.cdb
..........\..\cmp.pre_map.hdb
..........\..\cmp.psp
..........\..\cmp.rtlv.hdb
..........\..\cmp.rtlv_sg.cdb
..........\..\cmp.rtlv_sg_swap.cdb
..........\..\cmp.sgdiff.cdb
..........\..\cmp.sgdiff.hdb
..........\..\cmp.signalprobe.cdb
..........\..\cmp.sld_design_entry.sci
..........\..\cmp.sld_design_entry_dsc.sci
..........\..\cmp.syn_hier_info
..........\..\cmp.tan.qmsg
..........\..\cmp_cmp.qrpt

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