• To create Verilog-HDL module written in the RTL style appropriate for both simulation and synthesis, for an Asynchronous Serial Data Transmitter. • To verify the correct behaviour of the transmitter by means of simulation using a Verilog test-module. • To automatically create a logic diagram for the Asynchronous Serial Data Transmitter, generated using a Logic Synthesis tool.

TRL Design of a asynchronous bit serial data transmitter
........................................................\test_TXSysRTL.v
........................................................\TxSysRTL.ucf
........................................................\TxSysRTL.v

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