homework of VHDL course at SJTU

源代码
......\实验一-分频器设计
......\.................\clk_div.vhd
......\实验三-4位可逆计数器和转换器设计
......\................................\BICOUNTER.vhd
......\................................\GCODE.vhd
......\实验二-VHDL描述风格比较
......\.......................\MAJ1.vhd
......\.......................\MAJ2.vhd
......\.......................\MAJ3.vhd
......\.......................\MAJ4.vhd
......\实验八-数字密码锁的设计与实现
......\.............................\digilock.vhd
......\实验六-序列检测器的设计
......\.......................\fsm.vhd
......\实验四-7段数码管
......\................\segment7.vhd
......\................\SEGMENTCOUNT.vhd

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