VHDL CRC32 VHDL CRC32

CRC32
.....\.lso
.....\CRC16_HAOWQ.vhd
.....\CRC32.ise
.....\CRC32.ise_ISE_Backup
.....\CRC32.ntrc_log
.....\CRC32.restore
.....\crc_32.vhd
.....\pepExtractor.prj
.....\Signal.prj
.....\Signal.stx
.....\Signal.vhd
.....\Signal.xst
.....\Signal_summary.html
.....\Signal_vhdl.prj
.....\templates
.....\Test.cmd_log
.....\Test.lso
.....\Test.ngc
.....\Test.ngr
.....\Test.prj
.....\Test.stx
.....\Test.syr
.....\Test.xst
.....\TestBench.vhd
.....\TestBench_vhd.fdo
.....\TestBench_vhd.udo
.....\Test_summary.html
.....\Test_vhdl.prj
.....\transcript
.....\vsim.wlf
.....\work
.....\....\crc_32
.....\....\......\behavioral.dat
.....\....\......\behavioral.psm
.....\....\......\_primary.dat
.....\....\test
.....\....\....\behavioral.dat
.....\....\....\behavioral.psm
.....\....\....\_primary.dat
.....\....\testbench_vhd
.....\....\.............\behavior.dat
.....\....\.............\behavior.psm
.....\....\.............\_primary.dat
.....\....\_info
.....\....\_temp
.....\xst
.....\...\dump.xst
.....\...\........\Test.prj
.....\...\........\........\ngx
.....\...\........\........\...\notopt
.....\...\........\........\...\opt
.....\...\........\........\ntrc.scr
.....\...\file graph
.....\...\projnav.tmp
.....\...\work
.....\...\....\hdllib.ref
.....\...\....\hdpdeps.ref
.....\...\....\sub00
.....\...\....\.....\vhpl00.vho
.....\...\....\.....\vhpl01.vho
.....\...\....\.....\vhpl02.vho
.....\...\....\.....\vhpl03.vho
.....\_xmsgs
.....\......\xst.xmsgs

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