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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
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Introduction - If you have any usage issues, please Google them yourself
uart codes。write with vhdl.
Packet file list
(Preview for download)
用硬件VHDL语言实现的串口通信的试验代码
......................................\串口发送实验
......................................\............\串口发送实验
......................................\............\............\cmp_state.ini
......................................\............\............\db
......................................\............\............\..\add_sub_rdh.tdf
......................................\............\............\..\add_sub_udh.tdf
......................................\............\............\..\demo.asm.qmsg
......................................\............\............\..\demo.cbx.xml
......................................\............\............\..\demo.cmp.cdb
......................................\............\............\..\demo.cmp.hdb
......................................\............\............\..\demo.cmp.logdb
......................................\............\............\..\demo.cmp.rdb
......................................\............\............\..\demo.cmp.tdb
......................................\............\............\..\demo.cmp0.ddb
......................................\............\............\..\demo.dbp
......................................\............\............\..\demo.db_info
......................................\............\............\..\demo.eco.cdb
......................................\............\............\..\demo.fit.qmsg
......................................\............\............\..\demo.hier_info
......................................\............\............\..\demo.hif
......................................\............\............\..\demo.map.cdb
......................................\............\............\..\demo.map.hdb
......................................\............\............\..\demo.map.logdb
......................................\............\............\..\demo.map.qmsg
......................................\............\............\..\demo.pre_map.cdb
......................................\............\............\..\demo.pre_map.hdb
......................................\............\............\..\demo.psp
......................................\............\............\..\demo.pss
......................................\............\............\..\demo.rtlv.hdb
......................................\............\............\..\demo.rtlv_sg.cdb
......................................\............\............\..\demo.rtlv_sg_swap.cdb
......................................\............\............\..\demo.sgdiff.cdb
......................................\............\............\..\demo.sgdiff.hdb
......................................\............\............\..\demo.signalprobe.cdb
......................................\............\............\..\demo.sld_design_entry.sci
......................................\............\............\..\demo.sld_design_entry_dsc.sci
......................................\............\............\..\demo.smp_dump.txt
......................................\............\............\..\demo.sta.qmsg
......................................\............\............\..\demo.sta.rdb
......................................\............\............\..\demo.syn_hier_info
......................................\............\............\..\demo.tan.qmsg
......................................\............\............\..\demo_cmp.qrpt
......................................\............\............\..\demo_hier_info
......................................\............\............\..\demo_syn_hier_info
......................................\............\............\demo.asm.rpt
......................................\............\............\demo.bdf
......................................\............\............\demo.cdf
......................................\............\............\demo.done
......................................\............\............\demo.fit.eqn
......................................\............\............\demo.fit.rpt
........
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