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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 345kb
  • Downloaded :0次
  • Author :许***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
VERILOG a procedure on the FIFO. Very good.
Packet file list
(Preview for download)
fifo_2
......\db
......\..\fifo2.asm.qmsg
......\..\fifo2.asm_labs.ddb
......\..\fifo2.cbx.xml
......\..\fifo2.cmp.cdb
......\..\fifo2.cmp.hdb
......\..\fifo2.cmp.kpt
......\..\fifo2.cmp.logdb
......\..\fifo2.cmp.rdb
......\..\fifo2.cmp.tdb
......\..\fifo2.cmp0.ddb
......\..\fifo2.cmp2.ddb
......\..\fifo2.dbp
......\..\fifo2.db_info
......\..\fifo2.eco.cdb
......\..\fifo2.fit.qmsg
......\..\fifo2.hier_info
......\..\fifo2.hif
......\..\fifo2.map.cdb
......\..\fifo2.map.hdb
......\..\fifo2.map.logdb
......\..\fifo2.map.qmsg
......\..\fifo2.pre_map.cdb
......\..\fifo2.pre_map.hdb
......\..\fifo2.psp
......\..\fifo2.rtlv.hdb
......\..\fifo2.rtlv_sg.cdb
......\..\fifo2.rtlv_sg_swap.cdb
......\..\fifo2.sgdiff.cdb
......\..\fifo2.sgdiff.hdb
......\..\fifo2.signalprobe.cdb
......\..\fifo2.sld_design_entry.sci
......\..\fifo2.sld_design_entry_dsc.sci
......\..\fifo2.syn_hier_info
......\..\fifo2.tan.qmsg
......\fifo2.asm.rpt
......\fifo2.bdf
......\fifo2.bsf
......\fifo2.done
......\fifo2.fit.rpt
......\fifo2.fit.smsg
......\fifo2.fit.summary
......\fifo2.flow.rpt
......\fifo2.map.rpt
......\fifo2.map.smsg
......\fifo2.map.summary
......\fifo2.pin
......\fifo2.pof
......\fifo2.qpf
......\fifo2.qsf
......\fifo2.qws
......\fifo2.sof
......\fifo2.tan.rpt
......\fifo2.tan.summary
......\fifo2.v
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