6 bits risc cpu by Verilog

risc
....\alu.v
....\cpu.v
....\cpu_test.flow.rpt
....\cpu_test.map.rpt
....\cpu_test.map.summary
....\cpu_test.qpf
....\cpu_test.qsf
....\cpu_test.qws
....\cpu_test.v
....\db
....\..\cpu_test.cbx.xml
....\..\cpu_test.cmp.rdb
....\..\cpu_test.db_info
....\..\cpu_test.eco.cdb
....\..\cpu_test.hif
....\..\cpu_test.map.qmsg
....\..\cpu_test.map_bb.hdb
....\..\cpu_test.sld_design_entry.sci
....\..\cpu_test.tis_db_list.ddb
....\dram.v
....\exp.v
....\idec.v
....\incremental_db
....\..............\compiled_partitions
....\..............\README
....\pram.v
....\regs.v
....\risc.cr.mti
....\risc.mpf
....\risc8.vcd
....\vsim.wlf
....\work
....\....\alu
....\....\...\verilog.psm
....\....\...\_primary.dat
....\....\...\_primary.dbs
....\....\...\_primary.vhd
....\....\cpu
....\....\...\verilog.psm
....\....\...\_primary.dat
....\....\...\_primary.dbs
....\....\...\_primary.vhd
....\....\cpu_test
....\....\........\verilog.psm
....\....\........\_primary.dat
....\....\........\_primary.dbs
....\....\........\_primary.vhd
....\....\dram
....\....\....\verilog.psm
....\....\....\_primary.dat
....\....\....\_primary.dbs
....\....\....\_primary.vhd
....\....\exp
....\....\...\verilog.psm
....\....\...\_primary.dat
....\....\...\_primary.dbs
....\....\...\_primary.vhd
....\....\idec
....\....\....\verilog.psm
....\....\....\_primary.dat
....\....\....\_primary.dbs
....\....\....\_primary.vhd
....\....\pram
....\....\....\verilog.psm
....\....\....\_primary.dat
....\....\....\_primary.dbs
....\....\....\_primary.vhd
....\....\regs
....\....\....\verilog.psm
....\....\....\_primary.dat
....\....\....\_primary.dbs
....\....\....\_primary.vhd
....\....\_info
....\....\_temp
....\....\_vmake

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