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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 191kb
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  • Author :zhan*****
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Introduction - If you have any usage issues, please Google them yourself
8-bit parallel input into serial output digital conversion is based on the high-level hardware programming language VHDL prepared.
Packet file list
(Preview for download)
PiSo
....\db
....\..\PiSo.asm.qmsg
....\..\PiSo.asm_labs.ddb
....\..\PiSo.cbx.xml
....\..\PiSo.cmp.cdb
....\..\PiSo.cmp.hdb
....\..\PiSo.cmp.kpt
....\..\PiSo.cmp.logdb
....\..\PiSo.cmp.rdb
....\..\PiSo.cmp.tdb
....\..\PiSo.cmp0.ddb
....\..\PiSo.dbp
....\..\PiSo.db_info
....\..\PiSo.eco.cdb
....\..\PiSo.eds_overflow
....\..\PiSo.fit.qmsg
....\..\PiSo.fnsim.cdb
....\..\PiSo.fnsim.hdb
....\..\PiSo.fnsim.qmsg
....\..\PiSo.hier_info
....\..\PiSo.hif
....\..\PiSo.map.cdb
....\..\PiSo.map.hdb
....\..\PiSo.map.logdb
....\..\PiSo.map.qmsg
....\..\PiSo.pre_map.cdb
....\..\PiSo.pre_map.hdb
....\..\PiSo.psp
....\..\PiSo.rtlv.hdb
....\..\PiSo.rtlv_sg.cdb
....\..\PiSo.rtlv_sg_swap.cdb
....\..\PiSo.sgdiff.cdb
....\..\PiSo.sgdiff.hdb
....\..\PiSo.signalprobe.cdb
....\..\PiSo.sim.hdb
....\..\PiSo.sim.qmsg
....\..\PiSo.sim.rdb
....\..\PiSo.sim.vwf
....\..\PiSo.sld_design_entry.sci
....\..\PiSo.sld_design_entry_dsc.sci
....\..\PiSo.syn_hier_info
....\..\PiSo.tan.qmsg
....\..\wed.zsf
....\PiSo.asm.rpt
....\PiSo.done
....\PiSo.fit.rpt
....\PiSo.fit.smsg
....\PiSo.fit.summary
....\PiSo.flow.rpt
....\PiSo.map.rpt
....\PiSo.map.summary
....\PiSo.pin
....\PiSo.pof
....\PiSo.qpf
....\PiSo.qsf
....\PiSo.qws
....\PiSo.sim.rpt
....\PiSo.sof
....\PiSo.tan.rpt
....\PiSo.tan.summary
....\PiSo.vhd
....\PiSo.vwf
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