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beipin_top

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 99kb
  • Downloaded :0次
  • Author :刘****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Times verilog HDL code to describe the use of, 2 octave function can be achieved, but the frequency of a bit error.
Packet file list
(Preview for download)
beipin_top
..........\beipin0.v
..........\beipin1.v
..........\db
..........\..\top.asm.qmsg
..........\..\top.cbx.xml
..........\..\top.cmp.cdb
..........\..\top.cmp.hdb
..........\..\top.cmp.logdb
..........\..\top.cmp.rdb
..........\..\top.cmp.tdb
..........\..\top.cmp0.ddb
..........\..\top.dbp
..........\..\top.db_info
..........\..\top.eco.cdb
..........\..\top.eds_overflow
..........\..\top.fit.qmsg
..........\..\top.hier_info
..........\..\top.hif
..........\..\top.map.cdb
..........\..\top.map.hdb
..........\..\top.map.logdb
..........\..\top.map.qmsg
..........\..\top.pre_map.cdb
..........\..\top.pre_map.hdb
..........\..\top.psp
..........\..\top.pss
..........\..\top.rtlv.hdb
..........\..\top.rtlv_sg.cdb
..........\..\top.rtlv_sg_swap.cdb
..........\..\top.sgdiff.cdb
..........\..\top.sgdiff.hdb
..........\..\top.sim.cvwf
..........\..\top.sim.hdb
..........\..\top.sim.qmsg
..........\..\top.sim.rdb
..........\..\top.sld_design_entry.sci
..........\..\top.sld_design_entry_dsc.sci
..........\..\top.syn_hier_info
..........\..\top.tan.qmsg
..........\..\wed.wsf
..........\fenpin.v
..........\fenpin1.v
..........\top.asm.rpt
..........\top.done
..........\top.fit.rpt
..........\top.fit.summary
..........\top.flow.rpt
..........\top.map.rpt
..........\top.map.smsg
..........\top.map.summary
..........\top.pin
..........\top.pof
..........\top.qpf
..........\top.qsf
..........\top.qws
..........\top.sim.rpt
..........\top.sof
..........\top.tan.rpt
..........\top.tan.summary
..........\top.v
..........\top.vwf
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