Hot Search : Source embeded web remote control p2p game More...
Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog

4bitcomp

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 42kb
  • Downloaded :0次
  • Author :B*****
  • About : Nobody
  • PS : If download it fails, try it again. Download again for free!
Download1 Download2
Don't use download software fo downloading.
If download fail,Try it again for free.
Introduction - If you have any usage issues, please Google them yourself
I try 4-bit comparator here in VHDL
Packet file list
(Preview for download)
4bitcomp
........\4bitcomp.prj
........\component
........\constraint
........\coreconsole
........\designer
........\........\impl1
........\........\.....\simulation
........\hdl
........\...\4bitcomp.vhd
........\phy_synthesis
........\simulation
........\..........\modelsim.ini
........\..........\modelsim.log
........\..........\presynth
........\..........\........\a_4_bit_comparator
........\..........\........\..................\arch.dat
........\..........\........\..................\arch.dbs
........\..........\........\..................\arch.psm
........\..........\........\..................\_primary.dat
........\..........\........\..................\_primary.dbs
........\..........\........\stimulus
........\..........\........\........\stimulator.dat
........\..........\........\........\stimulator.dbs
........\..........\........\........\stimulator.psm
........\..........\........\........\_primary.dat
........\..........\........\........\_primary.dbs
........\..........\........\testbench
........\..........\........\.........\tbgeneratedcode.dat
........\..........\........\.........\tbgeneratedcode.dbs
........\..........\........\.........\tbgeneratedcode.psm
........\..........\........\.........\_primary.dat
........\..........\........\.........\_primary.dbs
........\..........\........\_info
........\..........\........\_temp
........\..........\run.do
........\..........\tb.log
........\..........\vsim.wlf
........\smartgen
........\........\smartgen.aws
........\stimulus
........\........\a_4_bit_comparator.dsk
........\........\a_4_bit_comparator.hpj
........\........\BtimErrors.log
........\........\files_to_build.txt
........\........\ModelUnderTest_tbench.btim
........\........\ModelUnderTest_tbench.vhd
........\........\waveperl.log
........\synthesis
........\viewdraw
........\........\sch
........\........\sym
........\........\vf
........\........\..\project.lst
........\........\viewdraw.ini
........\........\wir
Related instructions
  • We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
  • The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
  • Please use Winrar for decompression tools
  • If download fail, Try it againg or Feedback to us.
  • If downloaded content did not match the introduction, Feedback to us,Confirm and will be refund.
  • Before downloading, you can inquire through the uploaded person information

Nothing.

Post Comment
*Quick comment Recommend Not bad Password Unclear description Not source
Lost files Unable to decompress Bad
*Content :
*Captcha :
CodeBus is the largest source code store in internet!
Contact us :
1999-2046 CodeBus All Rights Reserved.