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61EDA_D721

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 29kb
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  • Author :zhao*****
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Introduction - If you have any usage issues, please Google them yourself
8* 8 multiplier design, and for all to share and learn from each other and progress together
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8*8的乘法器verilog源代码
...........................\lpm_mul
...........................\.......\lpm.cr.mti
...........................\.......\lpm.mpf
...........................\.......\lpm_mult.v
...........................\.......\lpm_mult.v.bak
...........................\.......\lpm_multtest.v
...........................\.......\lpm_multtest.v.bak
...........................\.......\transcript
...........................\.......\vsim.wlf
...........................\.......\work
...........................\.......\....\lpm_mult
...........................\.......\....\........\verilog.psm
...........................\.......\....\........\_primary.dat
...........................\.......\....\........\_primary.vhd
...........................\.......\....\lpm_multest
...........................\.......\....\...........\verilog.psm
...........................\.......\....\...........\_primary.dat
...........................\.......\....\...........\_primary.vhd
...........................\.......\....\_info
...........................\使用说明请参看右侧注释====〉〉.txt
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