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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 984kb
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Introduction - If you have any usage issues, please Google them yourself
FPGA to control the use of LCD. Procedures with two state machine
Packet file list
(Preview for download)
0804_Ctl_LCD
............\Ctl_LCD.asm.rpt
............\Ctl_LCD.bdf
............\Ctl_LCD.cdf
............\Ctl_LCD.done
............\Ctl_LCD.dpf
............\Ctl_LCD.fit.rpt
............\Ctl_LCD.fit.smsg
............\Ctl_LCD.fit.summary
............\Ctl_LCD.flow.rpt
............\Ctl_LCD.map.rpt
............\Ctl_LCD.map.summary
............\Ctl_LCD.pin
............\Ctl_LCD.pof
............\Ctl_LCD.qpf
............\Ctl_LCD.qsf
............\Ctl_LCD.qws
............\Ctl_LCD.sim.rpt
............\Ctl_LCD.sof
............\Ctl_LCD.tan.rpt
............\Ctl_LCD.tan.summary
............\Ctl_LCD.vwf
............\db
............\..\add_sub_6nh.tdf
............\..\add_sub_7nh.tdf
............\..\add_sub_olh.tdf
............\..\altsyncram_0431.tdf
............\..\Ctl_LCD.asm.qmsg
............\..\Ctl_LCD.cbx.xml
............\..\Ctl_LCD.cmp.cdb
............\..\Ctl_LCD.cmp.ecobp
............\..\Ctl_LCD.cmp.hdb
............\..\Ctl_LCD.cmp.hdb (无法打开)
............\..\Ctl_LCD.cmp.logdb
............\..\Ctl_LCD.cmp.rdb
............\..\Ctl_LCD.cmp.tdb
............\..\Ctl_LCD.cmp0.ddb
............\..\Ctl_LCD.cmp_bb.cdb
............\..\Ctl_LCD.cmp_bb.hdb
............\..\Ctl_LCD.cmp_bb.logdb
............\..\Ctl_LCD.cmp_bb.rcf
............\..\Ctl_LCD.dbp
............\..\Ctl_LCD.db_info
............\..\Ctl_LCD.eco.cdb
............\..\Ctl_LCD.eds_overflow
............\..\Ctl_LCD.fit.qmsg
............\..\Ctl_LCD.hier_info
............\..\Ctl_LCD.hif
............\..\Ctl_LCD.map.cdb
............\..\Ctl_LCD.map.ecobp
............\..\Ctl_LCD.map.hdb
............\..\Ctl_LCD.map.logdb
............\..\Ctl_LCD.map.qmsg
............\..\Ctl_LCD.map_bb.logdb
............\..\Ctl_LCD.pre_map.cdb
............\..\Ctl_LCD.pre_map.hdb
............\..\Ctl_LCD.psp
............\..\Ctl_LCD.pss
............\..\Ctl_LCD.rtlv.hdb
............\..\Ctl_LCD.rtlv_sg.cdb
............\..\Ctl_LCD.rtlv_sg_swap.cdb
............\..\Ctl_LCD.sgdiff.cdb
............\..\Ctl_LCD.sgdiff.hdb
............\..\Ctl_LCD.signalprobe.cdb
............\..\Ctl_LCD.sim.cvwf
............\..\Ctl_LCD.sim.hdb
............\..\Ctl_LCD.sim.qmsg
............\..\Ctl_LCD.sim.rdb
............\..\Ctl_LCD.sld_design_entry.sci
............\..\Ctl_LCD.sld_design_entry_dsc.sci
............\..\Ctl_LCD.smp_dump.txt
............\..\Ctl_LCD.syn_hier_info
............\..\Ctl_LCD.tan.qmsg
............\..\Ctl_LCD.tis_db_list.ddb
............\..\prev_cmp_Ctl_LCD.asm.qmsg
............\..\prev_cmp_Ctl_LCD.fit.qmsg
............\..\prev_cmp_Ctl_LCD.map.qmsg
............\..\prev_cmp_Ctl_LCD.qmsg
............\..\prev_cmp_Ctl_LCD.sim.qmsg
............\..\prev_cmp_Ctl_LCD.tan.qmsg
............\..\wed.wsf
............\fen50.bsf
............\fen50.v
............\fen50.v.bak
............\hailong.mif
............\LCD.bsf
............\LCD.v
............\LCD.v.bak
............\lpm_rom0.bsf
............\lpm_rom0.v
............\lpm_rom0_bb.v

............\lpm_rom0_waveforms.html
............\sopc_builder_log.txt
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