The purpose of this project is to design and simulate a parallel output controller (POC) which acts an interface between system bus and printer. The Altera’s Maxplus Ⅱ EDA tool is recommended and provided for simulation.

CPU
...\ACC.bsf
...\ACC.vhd
...\ALU.bsf
...\ALU.vhd
...\BR.bsf
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...\C.bsf
...\C.vhd
...\change.bsf
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...\change2.vhd
...\CPU.asm.rpt
...\CPU.bdf
...\CPU.done
...\CPU.fit.rpt
...\CPU.fit.summary
...\CPU.flow.rpt
...\CPU.map.rpt
...\CPU.map.summary
...\CPU.pin
...\CPU.pof
...\CPU.qpf
...\CPU.qsf
...\CPU.qws
...\CPU.sim.rpt
...\CPU.sof
...\CPU.tan.rpt
...\CPU.tan.summary
...\CPU.vwf
...\CPUdesign
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...\.........\br.acf
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...\.........\BR.sym
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...\.........\br.vhd
...\.........\control_unit.acf
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...\.........\control_unit.pin
...\.........\control_unit.pof
...\.........\control_unit.rpt
...\.........\control_unit.snf
...\.........\control_unit.sof
...\.........\CONTROL_UNIT.sym
...\.........\control_unit.ttf
...\.........\control_unit.vhd
...\.........\cpu.acf
...\.........\cpu.fit
...\.........\cpu.gdf
...\.........\cpu.hex
...\.........\cpu.hif
...\.........\cpu.mmf
...\.........\cpu.ndb
...\.........\cpu.pin
...\.........\cpu.pof

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