VHDL language with 8421 yards of the decimal counter, a state of change 0000-> 0001-> 0010-> 0011-> 0100-> 0101-> 0110-> 0111-> 1000-> 0000. Cycle.

计数器 8421
...........\cmp_state.ini
...........\count_deng.asm.rpt
...........\count_deng.done
...........\count_deng.fit.eqn
...........\count_deng.fit.rpt
...........\count_deng.fit.summary
...........\count_deng.flow.rpt
...........\count_deng.map.eqn
...........\count_deng.map.rpt
...........\count_deng.map.summary
...........\count_deng.pin
...........\count_deng.pof
...........\count_deng.qpf
...........\count_deng.qsf
...........\count_deng.qws
...........\count_deng.sim.rpt
...........\count_deng.tan.rpt
...........\count_deng.tan.summary
...........\count_deng.vhd
...........\count_deng.vwf
...........\db
...........\..\count_deng.asm.qmsg
...........\..\count_deng.cmp.cdb
...........\..\count_deng.cmp.ddb
...........\..\count_deng.cmp.hdb
...........\..\count_deng.cmp.rdb
...........\..\count_deng.cmp.tdb
...........\..\count_deng.db_info
...........\..\count_deng.fit.qmsg
...........\..\count_deng.hier_info
...........\..\count_deng.hif
...........\..\count_deng.map.cdb
...........\..\count_deng.map.hdb
...........\..\count_deng.map.qmsg
...........\..\count_deng.pre_map.hdb
...........\..\count_deng.project.hdb
...........\..\count_deng.rtlv.hdb
...........\..\count_deng.rtlv_sg.cdb
...........\..\count_deng.rtlv_sg_swap.cdb
...........\..\count_deng.sgdiff.cdb
...........\..\count_deng.sgdiff.hdb
...........\..\count_deng.sim.hdb
...........\..\count_deng.sim.qmsg
...........\..\count_deng.sim.rdb
...........\..\count_deng.sim.vwf
...........\..\count_deng.sld_design_entry.sci
...........\..\count_deng.sld_design_entry_dsc.sci
...........\..\count_deng.syn_hier_info
...........\..\count_deng.tan.qmsg
...........\..\count_deng_cmp.qrpt
...........\..\count_deng_sim.qrpt
...........\..\新建 文本文档.txt
...........\sim.cfg

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