the realization of verilog and VHDL code of the can bus interface

canbus
......\can_acf.v
......\can_bsp.v
......\can_btl.v
......\can_crc.v
......\can_defines.v
......\can_fifo.v
......\can_ibo.v
......\can_register.v
......\can_registers.v
......\can_register_asyn.v
......\can_register_asyn_syn.v
......\can_register_syn.v
......\can_testbench.v
......\can_testbench_defines.v
......\can_top.v
......\can_top_translate.vhd
......\timescale.v

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