This is a program written in VERILOG language can be run in the FPGA board. Have a significant role. Thank you.

count__10
.........\count__10.asm.rpt
.........\count__10.done
.........\count__10.fit.rpt
.........\count__10.fit.summary
.........\count__10.flow.rpt
.........\count__10.map.rpt
.........\count__10.map.summary
.........\count__10.pin
.........\count__10.qpf
.........\count__10.qsf
.........\count__10.qws
.........\count__10.sim.rpt
.........\count__10.tan.rpt
.........\count__10.tan.summary
.........\count__10.v
.........\count__10.vwf
.........\db
.........\..\add_sub_1sh.tdf
.........\..\count__10.asm.qmsg
.........\..\count__10.cbx.xml
.........\..\count__10.cmp.cdb
.........\..\count__10.cmp.hdb
.........\..\count__10.cmp.kpt
.........\..\count__10.cmp.logdb
.........\..\count__10.cmp.rdb
.........\..\count__10.cmp.tdb
.........\..\count__10.cmp0.ddb
.........\..\count__10.dbp
.........\..\count__10.db_info
.........\..\count__10.eco.cdb
.........\..\count__10.eds_overflow
.........\..\count__10.fit.qmsg
.........\..\count__10.fnsim.cdb
.........\..\count__10.fnsim.hdb
.........\..\count__10.fnsim.qmsg
.........\..\count__10.hier_info
.........\..\count__10.hif
.........\..\count__10.map.cdb
.........\..\count__10.map.hdb
.........\..\count__10.map.logdb
.........\..\count__10.map.qmsg
.........\..\count__10.pre_map.cdb
.........\..\count__10.pre_map.hdb
.........\..\count__10.psp
.........\..\count__10.rtlv.hdb
.........\..\count__10.rtlv_sg.cdb
.........\..\count__10.rtlv_sg_swap.cdb
.........\..\count__10.sgdiff.cdb
.........\..\count__10.sgdiff.hdb
.........\..\count__10.signalprobe.cdb
.........\..\count__10.sim.hdb
.........\..\count__10.sim.qmsg
.........\..\count__10.sim.rdb
.........\..\count__10.sim.vwf
.........\..\count__10.sld_design_entry.sci
.........\..\count__10.sld_design_entry_dsc.sci
.........\..\count__10.syn_hier_info
.........\..\count__10.tan.qmsg
.........\..\wed.zsf

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