RT8019 network controller in the FPGA design of the drive

l_standard_1c6
..............\button_pio.v
..............\cmp_state.ini
..............\connector_pll.bsf
..............\connector_pll.v
..............\connector_pll_bb.v
..............\cpu.ocp
..............\cpu.v
..............\cpu.vo
..............\cpu_jtag_debug_module.v
..............\cpu_jtag_debug_module_wrapper.v
..............\cpu_mult_cell.v
..............\cpu_ociram_default_contents.mif
..............\cpu_test_bench.v
..............\db
..............\..\add_sub_0qg.tdf
..............\..\add_sub_q4h.tdf
..............\..\add_sub_s4h.tdf
..............\..\altsyncram_bhc1.tdf
..............\..\altsyncram_bn41.tdf
..............\..\altsyncram_ei21.tdf
..............\..\altsyncram_gd41.tdf
..............\..\altsyncram_gpm1.tdf
..............\..\altsyncram_hd41.tdf
..............\..\altsyncram_ik01.tdf
..............\..\altsyncram_vkt1.tdf
..............\..\a_dpfifo_83p.tdf
..............\..\a_fefifo_7cf.tdf
..............\..\cntr_9c7.tdf
..............\..\cntr_df8.tdf
..............\..\cntr_rd8.tdf
..............\..\decode_9ie.tdf
..............\..\dpram_75p.tdf
..............\..\mult_add_ovq2.tdf
..............\..\scfifo_1to.tdf
..............\..\standard.asm.qmsg
..............\..\standard.cbx.xml
..............\..\standard.cmp.cdb
..............\..\standard.cmp.hdb
..............\..\standard.cmp.rdb
..............\..\standard.cmp.tdb
..............\..\standard.cmp0.ddb
..............\..\standard.db_info
..............\..\standard.eco.cdb
..............\..\standard.fit.qmsg
..............\..\standard.hier_info
..............\..\standard.hif
..............\..\standard.map.cdb
..............\..\standard.map.hdb
..............\..\standard.map.qmsg
..............\..\standard.pre_map.cdb
..............\..\standard.pre_map.hdb
..............\..\standard.psp
..............\..\standard.rtlv.hdb
..............\..\standard.rtlv_sg.cdb
..............\..\standard.rtlv_sg_swap.cdb
..............\..\standard.sgdiff.cdb
..............\..\standard.sgdiff.hdb
..............\..\standard.signalprobe.cdb
..............\..\standard.sld_design_entry.sci
..............\..\standard.sld_design_entry_dsc.sci
..............\..\standard.smp_dump.txt
..............\..\standard.syn_hier_info
..............\..\standard.tan.qmsg
..............\..\standard_cmp.qrpt
..............\delay_reset_block.bdf
..............\delay_reset_block.bsf
..............\E_RST.v
..............\ic_tag_ram.mif
..............\jtag_uart.v
..............\lcd.v
..............\onchip_ram_4K.hex
..............\onchip_ram_4K.v
..............\rca_cy1c12_board
..............\................\class.ptf
..............\................\system
..............\................\......\asmi.v
..............\................\......\cmp_state.ini
..............\................\......\cpu_0.ocp
..............\................\......\cpu_0.v
..............\................\......\cpu_0_test_bench.v
..............\................\......\data_RAM.hex
..............\................\......\data_RAM.v
..............\................\......\db
..............\................\......\..\altsyncram_7q01.tdf
..............\................\......\..\altsyncram_bhc1.tdf
..............\................\......\..\altsyncram_dno1.tdf
..............\................\......\..\altsyncram_np01.tdf
..............\................\......\..\altsyncram_q201.tdf
..............\................\......\..\altsyncram_ui01.tdf
..............\................\......\..\a_dpfifo_83p.tdf
..............\................\......\..\a_fefifo_7cf.tdf
..............\................\......\..\cntr_9c7.tdf
..............\................\......\..\cntr_rd8.tdf
..............\................\......\..\decode_9ie.tdf
..............\................\......\..\decode_fga.tdf
..............\................\......\..\dpram_75p.tdf
..............\................\......\..\mux_ecb.tdf
..............\................\......\..\rca_cy1c12_board.asm.qmsg
..............\................\......\..\rca_cy1c12_board.cbx.xml

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