Verilog hdl a UART-based serial port to receive subroutine.

uart_rxd
........\db
........\..\prev_cmp_uart_rxd.asm.qmsg
........\..\prev_cmp_uart_rxd.eda.qmsg
........\..\prev_cmp_uart_rxd.fit.qmsg
........\..\prev_cmp_uart_rxd.map.qmsg
........\..\prev_cmp_uart_rxd.qmsg
........\..\prev_cmp_uart_rxd.tan.qmsg
........\..\uart_rxd.asm.qmsg
........\..\uart_rxd.asm_labs.ddb
........\..\uart_rxd.cbx.xml
........\..\uart_rxd.cmp.bpm
........\..\uart_rxd.cmp.cdb
........\..\uart_rxd.cmp.ecobp
........\..\uart_rxd.cmp.hdb
........\..\uart_rxd.cmp.kpt
........\..\uart_rxd.cmp.logdb
........\..\uart_rxd.cmp.rdb
........\..\uart_rxd.cmp.tdb
........\..\uart_rxd.cmp0.ddb
........\..\uart_rxd.cmp2.ddb
........\..\uart_rxd.cmp_merge.kpt
........\..\uart_rxd.db_info
........\..\uart_rxd.eco.cdb
........\..\uart_rxd.eda.qmsg
........\..\uart_rxd.fit.qmsg
........\..\uart_rxd.hier_info
........\..\uart_rxd.hif
........\..\uart_rxd.lpc.html
........\..\uart_rxd.lpc.rdb
........\..\uart_rxd.lpc.txt
........\..\uart_rxd.map.bpm
........\..\uart_rxd.map.cdb
........\..\uart_rxd.map.ecobp
........\..\uart_rxd.map.hdb
........\..\uart_rxd.map.kpt
........\..\uart_rxd.map.logdb
........\..\uart_rxd.map.qmsg
........\..\uart_rxd.map_bb.cdb
........\..\uart_rxd.map_bb.hdb
........\..\uart_rxd.map_bb.logdb
........\..\uart_rxd.pre_map.cdb
........\..\uart_rxd.pre_map.hdb
........\..\uart_rxd.rtlv.hdb
........\..\uart_rxd.rtlv_sg.cdb
........\..\uart_rxd.rtlv_sg_swap.cdb
........\..\uart_rxd.sgdiff.cdb
........\..\uart_rxd.sgdiff.hdb
........\..\uart_rxd.sld_design_entry.sci
........\..\uart_rxd.sld_design_entry_dsc.sci
........\..\uart_rxd.syn_hier_info
........\..\uart_rxd.tan.qmsg
........\..\uart_rxd.tis_db_list.ddb
........\..\uart_rxd.tmw_info
........\..\uart_rxd_global_asgn_op.abo
........\..\wed.wsf
........\incremental_db
........\..............\compiled_partitions
........\..............\...................\uart_rxd.root_partition.cmp.atm
........\..............\...................\uart_rxd.root_partition.cmp.dfp
........\..............\...................\uart_rxd.root_partition.cmp.hdbx
........\..............\...................\uart_rxd.root_partition.cmp.kpt
........\..............\...................\uart_rxd.root_partition.cmp.logdb
........\..............\...................\uart_rxd.root_partition.cmp.rcf
........\..............\...................\uart_rxd.root_partition.map.atm
........\..............\...................\uart_rxd.root_partition.map.dpi
........\..............\...................\uart_rxd.root_partition.map.hdbx
........\..............\...................\uart_rxd.root_partition.map.kpt
........\..............\README
........\simulation
........\..........\modelsim
........\..........\........\gate_work
........\..........\........\.........\@c@y@c@l@o@n@e@i@i@i_@p@r@i@m_@d@f@f@e
........\..........\........\.........\......................................\verilog.psm
........\..........\........\.........\......................................\_primary.dat
........\..........\........\.........\......................................\_primary.dbs
........\..........\........\.........\......................................\_primary.vhd
........\..........\........\.........\@c@y@c@l@o@n@e@i@i_@p@r@i@m_@d@f@f@e
........\..........\........\.........\....................................\verilog.psm
........\..........\........\.........\....................................\_primary.dat
........\..........\........\.........\....................................\_primary.dbs
........\..........\........\.........\....................................\_primary.vhd
........\..........\........\.........\@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e
........\..........\........\.........\................................\verilog.psm
........\..........\........\.........\................................\_primary.dat
........\..........\........\.........\................................\_primary.dbs
........\..........\........\.........\................................\_primary.vhd
........\..........\........\.........\cycloneiii_and1
........\..........\........\.........\..............

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