Verilog hdl a UART-based serial port to send subroutine.

uart_txd
........\db
........\..\prev_cmp_uart_txd.asm.qmsg
........\..\prev_cmp_uart_txd.fit.qmsg
........\..\prev_cmp_uart_txd.map.qmsg
........\..\prev_cmp_uart_txd.qmsg
........\..\prev_cmp_uart_txd.tan.qmsg
........\..\uart_txd.asm.qmsg
........\..\uart_txd.asm_labs.ddb
........\..\uart_txd.cbx.xml
........\..\uart_txd.cmp.bpm
........\..\uart_txd.cmp.cdb
........\..\uart_txd.cmp.ecobp
........\..\uart_txd.cmp.hdb
........\..\uart_txd.cmp.kpt
........\..\uart_txd.cmp.logdb
........\..\uart_txd.cmp.rdb
........\..\uart_txd.cmp.tdb
........\..\uart_txd.cmp0.ddb
........\..\uart_txd.cmp2.ddb
........\..\uart_txd.cmp_merge.kpt
........\..\uart_txd.db_info
........\..\uart_txd.eco.cdb
........\..\uart_txd.fit.qmsg
........\..\uart_txd.hier_info
........\..\uart_txd.hif
........\..\uart_txd.lpc.html
........\..\uart_txd.lpc.rdb
........\..\uart_txd.lpc.txt
........\..\uart_txd.map.bpm
........\..\uart_txd.map.cdb
........\..\uart_txd.map.ecobp
........\..\uart_txd.map.hdb
........\..\uart_txd.map.kpt
........\..\uart_txd.map.logdb
........\..\uart_txd.map.qmsg
........\..\uart_txd.map_bb.cdb
........\..\uart_txd.map_bb.hdb
........\..\uart_txd.map_bb.logdb
........\..\uart_txd.pre_map.cdb
........\..\uart_txd.pre_map.hdb
........\..\uart_txd.rtlv.hdb
........\..\uart_txd.rtlv_sg.cdb
........\..\uart_txd.rtlv_sg_swap.cdb
........\..\uart_txd.sgdiff.cdb
........\..\uart_txd.sgdiff.hdb
........\..\uart_txd.sld_design_entry.sci
........\..\uart_txd.sld_design_entry_dsc.sci
........\..\uart_txd.syn_hier_info
........\..\uart_txd.tan.qmsg
........\..\uart_txd.tis_db_list.ddb
........\..\uart_txd.tmw_info
........\..\uart_txd_global_asgn_op.abo
........\..\wed.wsf
........\export
........\......\uart_txd.v
........\incremental_db
........\..............\compiled_partitions
........\..............\...................\uart_txd.root_partition.cmp.atm
........\..............\...................\uart_txd.root_partition.cmp.dfp
........\..............\...................\uart_txd.root_partition.cmp.hdbx
........\..............\...................\uart_txd.root_partition.cmp.kpt
........\..............\...................\uart_txd.root_partition.cmp.logdb
........\..............\...................\uart_txd.root_partition.cmp.rcf
........\..............\...................\uart_txd.root_partition.map.atm
........\..............\...................\uart_txd.root_partition.map.dpi
........\..............\...................\uart_txd.root_partition.map.hdbx
........\..............\...................\uart_txd.root_partition.map.kpt
........\..............\README
........\transcript
........\uart.cr.mti
........\uart.mpf
........\uart.v
........\uart_txd.asm.rpt
........\uart_txd.done
........\uart_txd.fit.rpt
........\uart_txd.fit.smsg
........\uart_txd.fit.summary
........\uart_txd.flow.rpt
........\uart_txd.map.rpt
........\uart_txd.map.summary
........\uart_txd.pin
........\uart_txd.pof
........\uart_txd.qpf
........\uart_txd.qsf
........\uart_txd.qws
........\uart_txd.sof
........\uart_txd.tan.rpt
........\uart_txd.v
........\uart_txd.v.bak
........\uart_txd.vht
........\uart_txd.vt
........\uart_txd.vwf
........\vsim.wlf
........\work
........\....\uart_txd_vlg_check_tst
........\....\......................\verilog.psm
........\....\......................\_primary.dat
........\....\......................\_primary.dbs
........\....\......................\_primary.vhd

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