Traffic light control system, including the UART module design and implementation of

traffic_light
.............\db
.............\..\prev_cmp_top.asm.qmsg
.............\..\prev_cmp_top.fit.qmsg
.............\..\prev_cmp_top.map.qmsg
.............\..\prev_cmp_top.tan.qmsg
.............\..\top.asm.qmsg
.............\..\top.cbx.xml
.............\..\top.cmp.bpm
.............\..\top.cmp.cdb
.............\..\top.cmp.ecobp
.............\..\top.cmp.hdb
.............\..\top.cmp.logdb
.............\..\top.cmp.rdb
.............\..\top.cmp.tdb
.............\..\top.cmp0.ddb
.............\..\top.cmp_bb.cdb
.............\..\top.cmp_bb.hdb
.............\..\top.cmp_bb.logdb
.............\..\top.cmp_bb.rcf
.............\..\top.dbp
.............\..\top.db_info
.............\..\top.eco.cdb
.............\..\top.fit.qmsg
.............\..\top.hier_info
.............\..\top.hif
.............\..\top.map.bpm
.............\..\top.map.cdb
.............\..\top.map.ecobp
.............\..\top.map.hdb
.............\..\top.map.logdb
.............\..\top.map.qmsg
.............\..\top.map_bb.cdb
.............\..\top.map_bb.hdb
.............\..\top.map_bb.logdb
.............\..\top.pre_map.cdb
.............\..\top.pre_map.hdb
.............\..\top.psp
.............\..\top.pss
.............\..\top.rtlv.hdb
.............\..\top.rtlv_sg.cdb
.............\..\top.rtlv_sg_swap.cdb
.............\..\top.sgdiff.cdb
.............\..\top.sgdiff.hdb
.............\..\top.signalprobe.cdb
.............\..\top.sld_design_entry.sci
.............\..\top.sld_design_entry_dsc.sci
.............\..\top.syn_hier_info
.............\..\top.tan.qmsg
.............\..\traffic_light.smp_dump.txt
.............\key_samble.v
.............\key_samble.v.bak
.............\key_sample
.............\..........\key_samble.v
.............\..........\key_samble.v.bak
.............\..........\key_sample.cr.mti
.............\..........\key_sample.mpf
.............\..........\key_sample_tb.v
.............\..........\key_sample_tb.v.bak
.............\..........\transcript
.............\..........\work
.............\..........\....\key_sample
.............\..........\....\..........\verilog.asm
.............\..........\....\..........\_primary.dat
.............\..........\....\..........\_primary.vhd
.............\..........\....\key_sample_tb
.............\..........\....\.............\verilog.asm
.............\..........\....\.............\_primary.dat
.............\..........\....\.............\_primary.vhd
.............\..........\....\_info
.............\key_sample_tb.v
.............\led8_disp.v
.............\led8_disp.v.bak
.............\led8_disp_tb.v
.............\pll.v
.............\prev_cmp_top.qmsg
.............\seven_seg_disp.v
.............\seven_seg_disp.v.bak
.............\seven_seg_disp_tb.v
.............\top.asm.rpt
.............\top.cdf
.............\top.done
.............\top.dpf
.............\top.fit.rpt
.............\top.fit.smsg
.............\top.fit.summary
.............\top.flow.rpt
.............\top.map.rpt
.............\top.map.smsg
.............\top.map.summary
.............\top.pin
.............\top.pof
.............\top.qsf
.............\top.sof
.............\top.tan.rpt
.............\top.tan.summary
.............\top.v
.............\top.v.bak
.............\traffic_lighe_tb.v
.............\traffic_lighe_tb.v.bak

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