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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 27kb
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  • Author :李***
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VHDL design with a stopwatch functions: stopwatch features include Start/PAUSE button and the Clear, 0.01 seconds to achieve accuracy, so count showed a total of eight digital tube, each of the digital control and eight-pin, so the use of scan ways to reduce the number of pins. Clock pulse from the lowest to the income, the use of asynchronous drive higher bit count, the clock frequency should be 100Hz, digital display, a total of eight digital tube, the scanning frequency should be 8 times higher than 100Hz. (Pay button Buffeting code elimination)
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EDA报告 24 李悦.doc
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