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seven_vote

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 125kb
  • Downloaded :0次
  • Author :梁****
  • About : Nobody
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this is a vote from seven people
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..........\all_add.asm.rpt
..........\all_add.bdf
..........\all_add.done
..........\all_add.fit.rpt
..........\all_add.fit.smsg
..........\all_add.fit.summary
..........\all_add.flow.rpt
..........\all_add.map.rpt
..........\all_add.map.summary
..........\all_add.pin
..........\all_add.pof
..........\all_add.qpf
..........\all_add.qsf
..........\all_add.qws
..........\all_add.sim.rpt
..........\all_add.sof
..........\all_add.tan.rpt
..........\all_add.tan.summary
..........\all_add.vwf
..........\db
..........\..\all_add.asm.qmsg
..........\..\all_add.cbx.xml
..........\..\all_add.cmp.cdb
..........\..\all_add.cmp.hdb
..........\..\all_add.cmp.kpt
..........\..\all_add.cmp.logdb
..........\..\all_add.cmp.rdb
..........\..\all_add.cmp.tdb
..........\..\all_add.cmp0.ddb
..........\..\all_add.dbp
..........\..\all_add.db_info
..........\..\all_add.eco.cdb
..........\..\all_add.fit.qmsg
..........\..\all_add.hier_info
..........\..\all_add.hif
..........\..\all_add.map.cdb
..........\..\all_add.map.hdb
..........\..\all_add.map.logdb
..........\..\all_add.map.qmsg
..........\..\all_add.pre_map.cdb
..........\..\all_add.pre_map.hdb
..........\..\all_add.psp
..........\..\all_add.pss
..........\..\all_add.rtlv.hdb
..........\..\all_add.rtlv_sg.cdb
..........\..\all_add.rtlv_sg_swap.cdb
..........\..\all_add.sgdiff.cdb
..........\..\all_add.sgdiff.hdb
..........\..\all_add.signalprobe.cdb
..........\..\all_add.sim.hdb
..........\..\all_add.sim.qmsg
..........\..\all_add.sim.rdb
..........\..\all_add.sim_ori.vwf
..........\..\all_add.sld_design_entry.sci
..........\..\all_add.sld_design_entry_dsc.sci
..........\..\all_add.syn_hier_info
..........\..\all_add.tan.qmsg
..........\..\wed.zsf
..........\seven_vote.bdf
..........\seven_vote.bsf
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