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A3P030_Decoder

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 236kb
  • Downloaded :0次
  • Author :宋****
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Introduction - If you have any usage issues, please Google them yourself
Actel A3p030 decoder
Packet file list
(Preview for download)
Decoder
.......\component
.......\.........\work
.......\.........\....\decoder_top
.......\.........\....\...........\decoder_top.cxf
.......\.........\....\...........\decoder_top.sdb
.......\.........\....\...........\decoder_top.v
.......\constraint
.......\coreconsole
.......\Decoder.prj
.......\designer
.......\........\impl1
.......\........\.....\ada00148-1.tmp
.......\........\.....\decoder_top.adb
.......\........\.....\decoder_top.dtf
.......\........\.....\...............\verify.log
.......\........\.....\decoder_top.ide_des
.......\........\.....\decoder_top.pdb
.......\........\.....\decoder_top.pdb.depends
.......\........\.....\decoder_top.tcl
.......\........\.....\decoder_top_fp
.......\........\.....\..............\$$FlashPro_FPBBALTLPT1.L$$
.......\........\.....\..............\decoder_top.log
.......\........\.....\..............\decoder_top.pro
.......\........\.....\..............\projectData
.......\........\.....\..............\...........\decoder_top.pdb
.......\........\.....\decoder_top_fp_1
.......\........\.....\................\$$FlashPro_FPBBALTLPT1.L$$
.......\........\.....\................\decoder_top.log
.......\........\.....\................\decoder_top.pro
.......\........\.....\................\projectData
.......\........\.....\................\...........\decoder_top.pdb
.......\........\.....\designer.log
.......\........\.....\simulation
.......\hdl
.......\...\KEY.v
.......\phy_synthesis
.......\simulation
.......\..........\modelsim.ini
.......\..........\modelsim.ini.sav
.......\smartgen
.......\........\Decoder
.......\........\.......\Decoder.cxf
.......\........\.......\Decoder.gen
.......\........\.......\Decoder.log
.......\........\.......\Decoder.v
.......\........\decoder_top_work.ixf
.......\........\Decoder_work.ixf
.......\........\KEY_work.ixf
.......\........\smartgen.aws
.......\stimulus
.......\synthesis
.......\.........\backup
.......\.........\......\Decoder.srr
.......\.........\......\decoder_top.srr
.......\.........\coreip
.......\.........\Decoder.areasrr
.......\.........\Decoder.edn
.......\.........\Decoder.map
.......\.........\Decoder.sdf
.......\.........\Decoder.so
.......\.........\Decoder.srd
.......\.........\Decoder.srm
.......\.........\Decoder.srr
.......\.........\Decoder.srs
.......\.........\Decoder.tlg
.......\.........\Decoder_sdc.sdc
.......\.........\Decoder_syn.prj
.......\.........\decoder_top.areasrr
.......\.........\decoder_top.edn
.......\.........\decoder_top.fse
.......\.........\decoder_top.htm
.......\.........\decoder_top.map
.......\.........\decoder_top.sap
.......\.........\decoder_top.sdf
.......\.........\decoder_top.so
.......\.........\decoder_top.srd
.......\.........\decoder_top.srm
.......\.........\decoder_top.srr
.......\.........\decoder_top.srs
.......\.........\decoder_top.tlg
.......\.........\decoder_top_sdc.sdc
.......\.........\decoder_top_syn.prj
.......\.........\run_options.txt
.......\.........\stdout.log
.......\.........\syntmp
.......\.........\......\Decoder.msg
.......\.........\......\Decoder.plg
.......\.........\......\decoder_top.msg
.......\.........\......\decoder_top.plg
.......\.........\......\decoder_top_flink.htm
.......\.........\......\decoder_top_srr.htm
.......\.........\......\decoder_top_toc.htm
.......\.........\......\sap.log
.......\viewdraw
.......\........\sch
.......\........\sym
.......\........\vf
.......\........\..\project.lst
.......\........\viewdraw.ini
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