LCD1602 driver in the development of FPGA design, software quartusII6.0, verilog

LCD1602显示
...........\db
...........\..\lcd1.asm.qmsg
...........\..\lcd1.asm_labs.ddb
...........\..\lcd1.cbx.xml
...........\..\lcd1.cmp.cdb
...........\..\lcd1.cmp.hdb
...........\..\lcd1.cmp.kpt
...........\..\lcd1.cmp.logdb
...........\..\lcd1.cmp.rdb
...........\..\lcd1.cmp.tdb
...........\..\lcd1.cmp0.ddb
...........\..\lcd1.cmp2.ddb
...........\..\lcd1.dbp
...........\..\lcd1.db_info
...........\..\lcd1.eco.cdb
...........\..\lcd1.fit.qmsg
...........\..\lcd1.hier_info
...........\..\lcd1.hif
...........\..\lcd1.map.cdb
...........\..\lcd1.map.hdb
...........\..\lcd1.map.logdb
...........\..\lcd1.map.qmsg
...........\..\lcd1.pre_map.cdb
...........\..\lcd1.pre_map.hdb
...........\..\lcd1.psp
...........\..\lcd1.rtlv.hdb
...........\..\lcd1.rtlv_sg.cdb
...........\..\lcd1.rtlv_sg_swap.cdb
...........\..\lcd1.sgdiff.cdb
...........\..\lcd1.sgdiff.hdb
...........\..\lcd1.signalprobe.cdb
...........\..\lcd1.sld_design_entry.sci
...........\..\lcd1.sld_design_entry_dsc.sci
...........\..\lcd1.smp_dump.txt
...........\..\lcd1.syn_hier_info
...........\..\lcd1.tan.qmsg
...........\lcd1.asm.rpt
...........\lcd1.cdf
...........\lcd1.done
...........\lcd1.dpf
...........\lcd1.fit.rpt
...........\lcd1.fit.smsg
...........\lcd1.fit.summary
...........\lcd1.flow.rpt
...........\lcd1.hexout
...........\lcd1.map.rpt
...........\lcd1.map.summary
...........\lcd1.pin
...........\lcd1.pof
...........\lcd1.qpf
...........\lcd1.qsf
...........\lcd1.qws
...........\lcd1.sof
...........\lcd1.tan.rpt
...........\lcd1.tan.summary
...........\lcd1602.v

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