Verilog hdl-based serial communication to achieve the series source

serial_verilog
..............\db
..............\..\serial_verilog.db_info
..............\..\serial_verilog.eco.cdb
..............\..\serial_verilog.sld_design_entry.sci
..............\serial.bsf
..............\serial.v
..............\serial_test.vhd
..............\serial_verilog.asm.rpt
..............\serial_verilog.bdf
..............\serial_verilog.cdf
..............\serial_verilog.done
..............\serial_verilog.fit.eqn
..............\serial_verilog.fit.rpt
..............\serial_verilog.fit.summary
..............\serial_verilog.flow.rpt
..............\serial_verilog.map.eqn
..............\serial_verilog.map.rpt
..............\serial_verilog.map.summary
..............\serial_verilog.pin
..............\serial_verilog.pof
..............\serial_verilog.qpf
..............\serial_verilog.qsf
..............\serial_verilog.qws
..............\serial_verilog.tan.rpt
..............\serial_verilog.tan.summary
..............\serial_verilog_assignment_defaults.qdf

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