University of Zurich, Switzerland, VHDL courseware. Of entry to some extent help the beginners.

瑞士苏黎世大学VHDL课件PPT_Tutorial_ETH
......................................\lecture0_organization.ppt
......................................\lecture10_ASM.ppt
......................................\lecture11_DLX.ppt
......................................\lecture1_intro.ppt
......................................\lecture2_dataflow_structural.ppt
......................................\lecture3_registers_counters.ppt
......................................\lecture4_FPGA_tools.ppt
......................................\lecture5_FSM.ppt
......................................\lecture6_mixed_RTL.ppt
......................................\lecture7_functions_memories_io.ppt
......................................\lecture8_timing_simulation.ppt
......................................\lecture9_types.ppt
......................................\project1_specification_1.ppt
......................................\project1_specification_2.ppt
......................................\project1_specification_3.ppt
......................................\project1_specification_4.ppt
......................................\project2_specification_1.ppt
......................................\project2_specification_2.ppt
......................................\project3_specification.ppt
......................................\使用说明请参看右侧注释====〉〉.txt

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