verilog

Verilog
.......\1.sequential_design.pdf
.......\10.7_behavioral.pdf
.......\11.basic_elements.pdf
.......\12.8_task_function.pdf
.......\13.9_useful_tech.pdf
.......\14.CaseStudy_MIPS32.pdf
.......\15.user_defined_Primitives.pdf
.......\16.switch.pdf
.......\17.delay.pdf
.......\2.ver_chap1.pdf
.......\3.ver_overview.pdf
.......\4.2_hierarchical.pdf
.......\5.basic_concept.pdf
.......\6.ver_examples.pdf
.......\7.4_module.pdf
.......\8.gatelevel.pdf
.......\9.6_dataflow.pdf
.......\ex2.doc
.......\Final Project Exercise 1.doc
.......\Final Project Exercise 2.doc
.......\Final Project Exercise 3.doc
.......\MIPS_ALU_exer4.v
.......\verilog code example.htm
.......\verilog-manual.htm
.......\verilog_manual1.htm
.......\ver_chap1.pdf
.......\ver_chap10_2up.pdf
.......\ver_chap11_2up.pdf
.......\ver_chap12_2up.pdf
.......\ver_chap1_2up.pdf
.......\ver_chap2_2up.pdf
.......\ver_chap3_2up.pdf
.......\ver_chap3_p1_2up.pdf
.......\ver_chap3_v2.pdf
.......\ver_chap4_2up.pdf
.......\ver_chap5.pdf
.......\ver_chap5_p1.pdf
.......\ver_chap6_2up.pdf
.......\ver_chap7_2up.pdf
.......\ver_chap8_2up.pdf
.......\ver_chap9_2up.pdf
.......\ver_examples-4up.pdf
.......\vlog_ref_body.html
.......\wires_in_verilog.htm

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