Unlimited divider, VHDL development, can be odd and even frequency.

20058002062李泉泉.doc
fre_div
.......\cmp_state.ini
.......\db
.......\..\fre_div.asm.qmsg
.......\..\fre_div.cbx.xml
.......\..\fre_div.cmp.cdb
.......\..\fre_div.cmp.hdb
.......\..\fre_div.cmp.rdb
.......\..\fre_div.cmp.tdb
.......\..\fre_div.cmp0.ddb
.......\..\fre_div.db_info
.......\..\fre_div.eco.cdb
.......\..\fre_div.eds_overflow
.......\..\fre_div.fit.qmsg
.......\..\fre_div.hier_info
.......\..\fre_div.hif
.......\..\fre_div.map.cdb
.......\..\fre_div.map.hdb
.......\..\fre_div.map.qmsg
.......\..\fre_div.pre_map.cdb
.......\..\fre_div.pre_map.hdb
.......\..\fre_div.psp
.......\..\fre_div.rpp.qmsg
.......\..\fre_div.rtlv.hdb
.......\..\fre_div.rtlv_sg.cdb
.......\..\fre_div.rtlv_sg_swap.cdb
.......\..\fre_div.sgate.rvd
.......\..\fre_div.sgdiff.cdb
.......\..\fre_div.sgdiff.hdb
.......\..\fre_div.signalprobe.cdb
.......\..\fre_div.sim.hdb
.......\..\fre_div.sim.qmsg
.......\..\fre_div.sim.rdb
.......\..\fre_div.sim.vwf
.......\..\fre_div.sld_design_entry.sci
.......\..\fre_div.sld_design_entry_dsc.sci
.......\..\fre_div.syn_hier_info
.......\..\fre_div.tan.qmsg
.......\..\fre_div_cmp.qrpt
.......\..\fre_div_sim.qrpt
.......\fre_div.asm.rpt
.......\fre_div.done
.......\fre_div.fit.eqn
.......\fre_div.fit.rpt
.......\fre_div.fit.summary
.......\fre_div.flow.rpt
.......\fre_div.map.eqn
.......\fre_div.map.rpt
.......\fre_div.map.summary
.......\fre_div.pin
.......\fre_div.pof
.......\fre_div.qpf
.......\fre_div.qsf
.......\fre_div.qws
.......\fre_div.sim.rpt
.......\fre_div.sof
.......\fre_div.tan.rpt
.......\fre_div.tan.summary
.......\fre_div.vhd
.......\fre_div.vwf
.......\pll.bsf
.......\pll.cmp
.......\pll.vhd
fre_div_1
.........\fre_div.prd
.........\fre_div.prj
.........\rev_1
.........\.....\.recordref
.........\.....\AutoConstraint_fre_div.sdc
.........\.....\backup
.........\.....\......\fre_div.srr
.........\.....\fre_div.fse
.........\.....\fre_div.htm
.........\.....\fre_div.map
.........\.....\fre_div.sap
.........\.....\fre_div.srd
.........\.....\fre_div.srm
.........\.....\fre_div.srr
.........\.....\fre_div.srs
.........\.....\fre_div.sxr
.........\.....\fre_div.szr
.........\.....\fre_div.tcl
.........\.....\fre_div.tlg
.........\.....\fre_div.vqm
.........\.....\fre_div.xrf
.........\.....\fre_div_cons.tcl
.........\.....\fre_div_rm.tcl
.........\.....\rpt_fre_div.areasrr
.........\.....\rpt_fre_div_areasrr.htm
.........\.....\run_options.txt
.........\.....\syntmp
.........\.....\......\fre_div.msg
.........\.....\......\fre_div.plg
.........\.....\......\fre_div_cons_ui.tcl
.........\.....\......\fre_div_flink.htm
.........\.....\......\fre_div_srr.htm
.........\.....\......\fre_div_toc.htm
.........\.....\......\sap.log
.........\.....\verif

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